_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<sb0> hi
<sb0> _florent_: litepcie is just a thin wrapper around the vendor proprietary IP, and there is currently no open source PCIe core that contains the full stack, correct?
<_florent_> sb0: LitePCIe provides a MMAP/DMA core around the integrated PCIe hard block, so it's not handling the lower layers of PCIe and start operating at the TLP layer.
<_florent_> so the goals are similar to Xillibus, RIFFA, etc... so it's indeed a thin wrapper in a similar way a USB3 Core is a thin wrapper around a USB3 PIPE, just a matter of connecting wires together :)
<_florent_> i'm not aware of an open source PCIe PHY, but there is a current GSoC project on that
<sorear> (what's the gsoc thing?)
<tpb> Title: GitHub - whitequark/Yumewatari: 妖刀夢渡 (at github.com)
<_florent_> sorear: sorry i was trying to find it, it's https://github.com/ECP5-PCIe
<tpb> Title: ECP5-PCIe · GitHub (at github.com)
<sorear> oh good, the existing work is being used as a base
<_florent_> yes, from what i understand, it has been converted from Migen to nMigen and will now go further
<zyp> hmm, apparently the cle-215 heatsink is glued to the fpga?
<_florent_> zyp: i haven't tried personnally but it seems others have been able to remove the heatsink without damaging the FPGA: https://www.eevblog.com/forum/fpga/sqrl-acorn-as-an-interesting-artix-7-board/msg3053338/#msg3053338
<tpb> Title: SQRL Acorn as an interesting Artix-7 board? - Page 2 (at www.eevblog.com)
<zyp> ah, right
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<keesj> hi
<_florent_> keesj: hi
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<daddesio> ECP5-5G doesn't have PCIe/DDR/USB hard blocks, right? it's just soft cores built atop the SERDES?
<daveshah> Yes, although DDR doesn't use the SERDES it uses the gearbox
<daveshah> SERDES in ECP5 is the high speed 5Gbps thingy, not the thing that is on every IO pin
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