<mithro>
Xilinx just published a copy of their Unisim library (normally found in vivado) on GitHub under an Apache 2.0 license! https://github.com/Xilinx/XilinxUnisimLibrary -- next step is to get them to run in iverilog and/or verilator
<benh>
mithro: now if only they also published a VHDL one :-)
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<benh>
_florent_: do that ring a bell
<benh>
LiteDRAM built from Migen b1b2b29 and LiteX 28ea4b3f
<benh>
m0: |000000000000001111111111| delay: 14
<benh>
m2: |000000000001111111111111| delay: 11
<benh>
m1: |000000000000001111111111| delay: 14
<benh>
m3: |000000000011111111111111| delay: 10
<benh>
(hang)
<benh>
this is standalone microwatt with a litedram generated for Genesys2 (with a 100Mhz sys_clk from the 200Mhz input)
<benh>
using modified version of genesys2.yml from litedram examples
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<_florent_>
benh: i probably already saw this but was not able to reproduce it easily to investigate. If you are able to easily reproduce it on the Genesys2, can you create a PR on LiteDRAM repo with the required files? i could look at this
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<benh>
_florent_: it's a user trying microwatt standalone with stuff I generated so it's a bit tricky ... there are other weird problems though, some of the stuff the code displays makes no sense (some of my stuff, like it reads some internal config register I have on my wishbone and that seems to return 0 ... but it's hard wired via a generic to some other value and the vivado logs seem to indicate the generic was bound properly ... so a mystery at this point :)
<benh>
_florent_: might be worth asking him to try with LiteX I suppose ...
<benh>
the main difference I noticed is that standalone litedram generates a PLL while LiteX generates an MMCM, the formers has unused "dq" clock outputs but I don't see why any of htat would be a problem (I double checked the configs, they seem fine)
<benh>
oh and LiteX runs at 125Mhz on the genesys while I run at 100 at the moment
<benh>
but I don't have a board to test and investigate myself so ...
<benh>
oh... he didn't wire the cs_n pins of the DRAM in his toplevel ...
<benh>
_florent_: btw, on a different note, you know about FPGAs... :-)
<benh>
_florent_: in microwatt, for historical reasons, we define our wishbones with address bits all the way down to 0 such as the bottom bits are "byte address" and are unused... ie on a 32-bit wishbone we have 2 unused bottom bits and on a 64-bit one, 3
<_florent_>
benh: ok for the issue on the Genesys2, just in case there is an easy repro, i have this board so could help
<benh>
_florent_: I've been meaning to clean that up for a while ... so I just did (effectively made all the arrays be N downto 2 or N downto 3)
<benh>
and reduced various latches accordingly
<benh>
and the end result after going through vivado is increased LUT and register utilization
<benh>
can you think of any reason for this ?
<benh>
_florent_: ok thanks. I'll have him try LiteX first and fix a few things in his toplevel
<benh>
_florent_: and if we don't get to the bottom of it, I'll merge his stuff in a branch you can try out if you feel like messing around with standalone mw :)
<_florent_>
benh: in fact that's probably better to use byte addressing on any buses, this makes integration a lot easier and avoid errors/confusions. The wishbone bus in LiteX uses word addressing for historical reason, but i'm no longer sure it was a good choice
<_florent_>
benh: that's indeed sometimes difficult to relate logic changes with Vivado's Luts/Register utilization. Very subtles changes can allow it/prevent it to/from optimizing things, the log would need to be carefully analyzed
<benh>
_florent_: thanks. The logs aren't always that clear but yes ... I think I'll leave it as it was then
<benh>
it does make the decoders easier and more readable indeed :)
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<jaseg>
I'm playing around with litex (master) and its vivado backend for artix 7 and vivado fairly frequently crashes ("abnormal program termination" or outright segfaults). Is this expected behavior or is my vivado setup b0rked?
<jaseg>
Simply re-running the same command usually works though.
<tpb>
Title: PCB800661 Single HDMI Drive Board HDMI to LVDS Adapter Board LCD Screen Drive Plate 7 Inch 42 Inch|Air Conditioner Parts| - AliExpress (at www.aliexpress.com)
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<lf>
CarlFK: i am new to this. but i would say driveing the lvds display should be possoble, but you might need to remove the 5v buffer and add voltage divider to match 3.3 to 1.8V
<lf>
what is the image source HDMI or ethernet?
<CarlFK[m]>
Eathernet. Or rendered by the fpga based on something coming in over ethernet
<satnav>
hello everyone, Can someone please suggest me any documentation or tutorial with how to build simple SoC and documentation about the different modules in LiteX? Thanks in advance!
<tpb>
Title: FPGA Tomu Workshop FPGA Tomu (Fomu) Workshop 0.1-192-ga639335 documentation (at workshop.fomu.im)
<satnav>
thanks zyp and CarlFK!
<zyp>
which board do you have? I personally found the easiest way to be building an existing example for a board I had and then pick it apart to figure out how stuff fit together
<satnav>
I have platform with Lattice ICE40HX1K. it kind of like the "icebreaker" platform.
<zyp>
icestick?
<satnav>
Go board from nandland
<zyp>
ah
<satnav>
I wonder if ICE40HX1K has enough logic to contain RISC-V soft-core (like SERV) and UART. it has 1K LUTs. do you have any experience with ICE40HX1K and LiteX?
<zyp>
I've used litex on the icestick, but without a cpu, haven't checked whether SERV would fit
<zyp>
gonna give it a try :)
<satnav>
nice :)
<satnav>
zyp Do you have the code with LiteX on icestick in GitHub? It will be great to see it
<zyp>
no, it's just a pile of mess :)
<zyp>
I'll upload the serv stuff if I can get it to work
<satnav>
keep update :)
<zyp>
okay, problem 1 is that hx1k only have 8kB of block ram in total, litex bios as it builds requires more
<zyp>
but building without that, it works :)
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<zyp>
you can remove the «import deps», that's just some stuff I've got to set up the pythonpath
<zyp>
with --no-compile-software, it builds here, 76% utilization of a hx1k
<zyp>
and then you just need to figure out how to load some software into it :)
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<satnav>
nice zyp! thanks!
<zyp>
SoCCore has an argument called integrated_rom_init, so I guess you could just provide the firmware image there
<zyp>
_florent_ has been talking about making it easier to boot directly into other software than the litex bios, but I'm not sure what the current status of that is
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