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<npcomp>
_florent_ dkozel Hi! Very new to the community here, I have had a latent interest in FPGA for some time, but was always previously deterred by form factor or price.
<npcomp>
I saw your tweet/discussion on the CLE 215 from SQRL, and along with finding some other resources online, decided to spring for one.
<npcomp>
Excited to potentially joing the party, but looks like I still need to locate my JTAG adapter?
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<_florent_>
npcomp: Hi and welcome, the CLE 215 is indeed a nice FPGA board. For now you will need a JTAG adapter, it would be possible to reverse engineer the gateware update protocol over PCIe, but not sure it's worth doing it since JTAG pins are available and documented.
<CarlFK>
xobs: (or _florent_) can/is the gpio stuff on the pi standard jtag that could be used with just some jumper wires?
<awordnot>
for my CLE 215 I just ended up buying the mating connector and some precrimped wires from digikey, then I cut them in half and soldered the other end to a standard 2.54mm header
<awordnot>
I'm using the digilent HS3 jtag adapter which supports vivado, but if you were using OpenOCD I think you could use anything
<zyp>
I did the same, planning to use a generic ft232h adapter
<zyp>
… if my CLE 215 ever arrives, it's been stuck in the mail for weeks now
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<npcomp>
I think the easiest OpenOCD-compatible board might be a bus pirate I have close at hand, but to be honest I haven't really done much with openocd
<npcomp>
> it would be possible to reverse engineer the gateware update protocol over PCIe
<npcomp>
I was wondering if there was a good place to document stock gateware on the board, and continuing work that might take place on it.