_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<_florent_> somlo: thanks for the feedback on 32-bit CSR alignment, i'm going to continue looking a bit a LiteSDCard (still at gateware/firmware level) and will also try to have a closer look at your ECP5 PHY.
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<somlo> _florent_: now that you merged litesdcard PR #10, this is the reason I couldn't just make it work by "pattern matching" ODDRs between xilink and ecp5: https://imgur.com/a/Q4RKsa6
<tpb> Title: Imgur: The magic of the Internet (at imgur.com)
<somlo> (thanks to daveshah for actually pointing out the problem)
<_florent_> somlo: ah thanks, that will be useful
<_florent_> have you been able to make it work?
<somlo> never had enough peace from $DAYJOB to actually focus on the migen :) So no, sorry
<_florent_> ok, i was going to look at that
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<_florent_> somlo: litesdcard is now working on ECP5 :), see https://github.com/enjoy-digital/litesdcard/pull/10#issuecomment-638316671
<tpb> Title: RFC: phy: add support for Lattice ECP5 (SDPHYIOECP5) by gsomlo · Pull Request #10 · enjoy-digital/litesdcard · GitHub (at github.com)
<_florent_> somlo: i only tested on ULX3S, could you do the test on the trellisboard?
<somlo> _florent_: saw the email from github, am in the process of patching litex-boards/.../trellisboard.py to test :)
<somlo> will send updated PR for trellisboard once I get it working
<_florent_> somlo: ok good thanks.
<_florent_> ok my side i'm trying to see if i can boot linux from it (as we were doing with SPI mode, but with SD mode this time)
<somlo> once I get the linux driver to work on rocket, I want to try actually mounting a linux FS and comparing usability (in terms of read/write speed)
<somlo> maybe systemd on Fedora will no longer throw its hands up during initrd :)
<somlo> and thanks for the ECP5 sdcard patches, forgot to mention that :D
<_florent_> somlo: for now i'm not sure you'll see spectacular improvements, but let's make it working first and we'll improve it. With an increase of the frequency (fixed to 10MHz now) and a rework of the Mem data writer/readers, it should be a lot faster
<somlo> oh, I forgot about the 10MHz hardcoded clock :) But I can try hardcoding it to something higher (not as a long-term solution, but as a quick and dirty hack :D )
<_florent_> if your SDCard is initializing with a higher frequency it should be fine yes
<somlo> _florent_: works with rocket on the trellisboard as well: https://github.com/litex-hub/litex-boards/pull/79
<tpb> Title: targets/trellisboard: add initial LiteSDCard support by gsomlo · Pull Request #79 · litex-hub/litex-boards · GitHub (at github.com)
<_florent_> somlo: great, thanks for the test and PR
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<somlo> well, crap... Sometimes, when the gateware verilog is "just right", I end up running into this abc issue: https://github.com/berkeley-abc/abc/issues/84
<tpb> Title: double free or corruption error during yosys abc9 techmap pass · Issue #84 · berkeley-abc/abc · GitHub (at github.com)
<somlo> It happened for rocket on ecp5versa for a while, then after some changes it stopped. Now it started happening on the rocket + trellisboard combo
<somlo> trying without "-abc9" on the yosys synth_ecp5 command line, curious what happens then
<somlo> maybe `abc9` should be optional...
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