13:31 <acathla> Why do we have 8 bits CSR on a 32 bits VexRiscv ? #define CONFIG_CSR_DATA_WIDTH 8

14:31 <_florent_> acathla: it's still the default, but this could be changed now that the different cores have been validated with it.

14:32 <_florent_> i'm going to change it

14:34 <acathla> Ok, nice.

14:38 <_florent_> done :): https://github.com/enjoy-digital/litex/commit/898743c344d53568b98e4e4c225067659711303c

14:38 <tpb> Title: soc: change default CSR bus data-width to 32. · enjoy-digital/litex@898743c · GitHub (at github.com)

14:46 <acathla> Perfect! Merci =)

14:52 <acathla> oh, you pushed the changes to the fomu target. Do you know why SPI works in 1x while it should be in 4x like in foboot?

14:53 <acathla> may be xobs knows why...

14:54 <xobs> No idea. Maybe something got changed upstream with Hacker vs PVT revisions?

14:59 <acathla> _florent_ based it on icebreaker, may be icebreaker just has 1x SPI that's all

15:00 <acathla> Hum, no, SpiFlash(platform.request("spiflash4x"), dummy=6, endianness="little")

15:00 <_florent_> acathla: i've not yet been able to get it working in 4x mode (but i haven't spent a lot of time on this), but i'm planning to look a this for both iCEBreaker and Fomu

15:01 <_florent_> acathla: it's possible i was just using a wrong dummy cycle

15:08 <acathla> I don't know how to choose the right dummy cycle... I tried one config but failed too.

15:21 <_florent_> On Fomu/PVT it should be 6, but i suspect there is something else

15:35 <scientes> If you have Fomu building I would love to hear how

15:41 <acathla> scientes, new version, you just need to get and modify a bit a file of valentyusb

16:02 <acathla> Is it normal I cannot read back a CSRStorage ?

16:05 <acathla> may be it's CSRAccess.ReadOnly by default...

16:17 <acathla> CSRField("tx_power", offset= 8, size=2, reset=1, access=CSRAccess.WriteOnly, description="Transmition power, 0 is off, 3 is the maximum"),

16:17 <acathla> It says : assert access is None or (access in CSRAccess.values())

16:17 <acathla> how do I fill the access= field?!

16:26 <acathla> _florent_, did you try this?