_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<acathla> Why do we have 8 bits CSR on a 32 bits VexRiscv ? #define CONFIG_CSR_DATA_WIDTH 8
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<_florent_> acathla: it's still the default, but this could be changed now that the different cores have been validated with it.
<_florent_> i'm going to change it
<acathla> Ok, nice.
<tpb> Title: soc: change default CSR bus data-width to 32. · enjoy-digital/litex@898743c · GitHub (at github.com)
<acathla> Perfect! Merci =)
<acathla> oh, you pushed the changes to the fomu target. Do you know why SPI works in 1x while it should be in 4x like in foboot?
<acathla> may be xobs knows why...
<xobs> No idea. Maybe something got changed upstream with Hacker vs PVT revisions?
<acathla> _florent_ based it on icebreaker, may be icebreaker just has 1x SPI that's all
<acathla> Hum, no, SpiFlash(platform.request("spiflash4x"), dummy=6, endianness="little")
<_florent_> acathla: i've not yet been able to get it working in 4x mode (but i haven't spent a lot of time on this), but i'm planning to look a this for both iCEBreaker and Fomu
<_florent_> acathla: it's possible i was just using a wrong dummy cycle
<acathla> I don't know how to choose the right dummy cycle... I tried one config but failed too.
<_florent_> On Fomu/PVT it should be 6, but i suspect there is something else
<scientes> If you have Fomu building I would love to hear how
<acathla> scientes, new version, you just need to get and modify a bit a file of valentyusb
<acathla> Is it normal I cannot read back a CSRStorage ?
<acathla> may be it's CSRAccess.ReadOnly by default...
<acathla> CSRField("tx_power", offset= 8, size=2, reset=1, access=CSRAccess.WriteOnly, description="Transmition power, 0 is off, 3 is the maximum"),
<acathla> It says : assert access is None or (access in CSRAccess.values())
<acathla> how do I fill the access= field?!
<acathla> _florent_, did you try this?
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