_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<nickoe> zyp: Hmm! Can it be because I am trying to access the memory in the very first cycles that it does not work? Maybe the memory is not initialized, even in the sim?
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<zyp> maybe, I've never tried simulating memory
<nickoe> I just tried to use the DMAReader from the from litevideo.output.core import DMAReader, and I appear to see the same issue of zero data
<nickoe> I mean, that is how I did it initally
<nickoe> which does not appear to work
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<nickoe> mmm, please remind me how to make the litex_server connect to my simulation
<nickoe> I am trying litex_server --udp but I get Exception: Unable to probe Etherbone server at 192.168.1.50.
<nickoe> I have --with-etherbone for my sim
<nickoe> zyp: Ok, I now got some data. I made it trace on demand from the demo app.. and when I write ot the CSR storage bit i will start the dma and trace it
<nickoe> it appears I have the correct data initally, but I may not be dumping the data correctly in the demo app https://i.snipboard.io/7CrtjT.jpg
<nickoe> I am not exactly sure I understand why there is that much spacing between the bytes
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<nickoe> Can gtkwave count transistions, like or example if I quicly want to count cyles on a signal without having to calculate it from the time?
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<Melkhior> Hello all,
<Melkhior> Got around reimplementing the PS/2 host controller in Migen to make it easier to use in Litex.Not sure how to 'properly' integrate it in Litex (namespace, which repository or in its own, ...) and that's my first Migen code so it's probably quite ugly. But it enables me to have a proper text console when using a framebuffer in Linux :-)
<Melkhior> Repo with current code, Linux driver, and example of how I intergrated it in my board are in: https://github.com/rdolbeau/PS2forLitex
<Melkhior> Any advice on integration/cleanup/improvement welcome!
<nickoe> Melkhior: cool, but I have no idea where to contribute that
<nickoe> Melkhior: Do you have a video demo?
<nickoe> asuming you tested it on hw
<Melkhior> no video sorry, tested on my Qmtech Wukong (cheap chinese-made Artix-7 100T board) with a digilent PS/2 Pmod and an old PS/2 keyboard I have lying around
<nickoe> zyp: Do you know how I can make better use of the time with the LiteDRAMDMAReader()? I just get four bytes at a time here https://i.snipboard.io/FDtqxm.jpg
<Melkhior> untested with a mouse because I haven't found a PS/2 mouse i my archives (the PS/2 keyboard was for older servers, no need for a matching mouse)
<Melkhior> linux says:
<Melkhior> buildroot:~> dmesg | grep kbd
<Melkhior> [ 2.839894] litex_ps2 f0004800.ps2kbd: base (ptrval), irq 3
<Melkhior> [ 3.710142] input: AT Raw Set 2 keyboard as /devices/platform/soc/f0004800.ps2kbd/serio0/input/input0
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<nickoe> mmm, how do I do bitwise operations on signals in migen?
<nickoe> slike OR a slice together with another signal
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<nickoe> I tried to make this, probably ridiculously complex way of doing this, https://dpaste.com/FDRXYC66G.txt ... which does not work as expected.
<nickoe> It is about the two orange sigals, I wanted to concatenate the single bytes into a 32 bit signal.
<nickoe> I clearly failed at it so far.
<nickoe> mmm, I think I got it, missing the MSB
<nickoe> in the slice
<Melkhior> @nickoe yes in Migen they are Python slice so the upper bound is not included
<Melkhior> I got bit by that one as well
<nickoe> So I got the indexing right now, but I don
<nickoe> don't understand why the other bits are set to zero when I just .eq a slice.
<Melkhior> and 'Cat' to concatenate is lsb->msb, reverse from verilog's '{}' notation
<Melkhior> I don't know enough migen to help sorry
<Melkhior> maybe try with NextValue and copying the old values ?
<Melkhior> NextValue(data, Cat(newdata[0:8], data[8:32]))
<Melkhior> to replace the low-order 8 bits?
<Melkhior> good luck
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