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<_florent_>
nickoe: you use-case should be very similar to what is done in the VideoFramebuffer: LiteDRAMDMAReader (with native Data Width) --> 1) Clock Domain Crossing --> 2) Data Width Conversion to 32-bit. (1) and 2) order can be swapped depending on the Data Width and clock frequencies): https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/video.py#L605-L636
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<RaivisR>
finally got one of the ddr3 chips cooperating on ecp5 vip, the trick was to force bank 7 vref to be used
<RaivisR>
also, using diamond to build and found that all pin constraints should be placed in single Misc(), otherwise Diamond takes the last one and resets all the other values to defaults for that last constraint
<_florent_>
RaivisR: ah good
<RaivisR>
learning as I go, next step, both chips
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<RaivisR>
ok, now both chips work and with both toolchains, trellis and diamond
<RaivisR>
at sys_clk 50MHz
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<zyp>
_florent_, figured out the qspi problems I were having yesterday -- the flash chip on ecpix-5 (IS25LP256D) requires a «quad enable» bit to be set in the status register, otherwise it simply won't respond to the quad read command
<zyp>
I just tried the ulx3s as a sanity check, and that just worked
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<zyp>
reading a bit further up on it, it's non-volatile and most qspi flash chips appears to have the same, so it's just a matter of how it's been initialized
<zyp>
s/the same/the equivalent/
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<_florent_>
zyp: ah ok, I also remember spending some time on this on other boards, we should maybe add some comments in the core to check this
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<nickoe>
_florent_: hmm, cool. Using, self.comb += self.dma.source.connect(self.cdc.sink) does that also connect other signals like ready and valid up?
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<zyp>
nickoe, yes
<nickoe>
hmm
<zyp>
you can picture x.connect(y) as shorthand for y.data.eq(x.data), y.valid.eq(x.valid), x.ready.eq(y.ready) and so on
<zyp>
plus last/first
<nickoe>
I better try that, it should make it a lot simpler.
<nickoe>
But how do I control incrementing my address signal correctly then?
<zyp>
use connect when you're connecting endpoints to each other, use eq when you're manipulating the individual signals of an endpoint
<zyp>
you should probably have an address generator module with a source endpoint that outputs adresses
<zyp>
then you'll use eq inside the module to set the signals of the endpoint, and connect on the outside to connect this module to other modules
<nickoe>
I am not sure I understand the Endpoint()'s yet
<zyp>
an endpoint is essentially just a record for a stream
<zyp>
and a record is just a collection of signals
<nickoe>
Does the AsyncFIFO have an endpoint defined alread?
<zyp>
so a source endpoint is a collection of signals for a stream output from a module
<zyp>
yeah, AsyncFIFO has a sink and a source
<leons>
I'm currently working on some custom VexRiscv CPU configurations. I've noticed when starting from the "Secure" Vex variant and disabling caches (instruction and data) the bootloader will hang at "Booting from boot.json..." indefinitely
<leons>
Is this a known issue? Will try to reproduce on a clean LiteX head and standard board tomorrow