_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<essele> Hi all ... just starting with this & following instructions have got a standard bitstream built ... but there is no timing report, how do I get timing info? (just did ./radiona_ulx3s.py --build)
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