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<Melkhior>
@gsomlo Darn, wanted to try the new sdcard w/ interrupt, but some recent Linux changes in Kconfig broke the kconfiglib.py used by Yocto :-(
<Melkhior>
Is there some way to use an older kernel version with the Litex stuff on litex-rebase ?
<Melkhior>
I probably shoud bite the bullet and figure out to generate a working kernel on my own (w/o buildroot or yocto)
<Quarky93[m]>
_florent_: sorry to bother again, were you able to get HBM running? I'm not very familiar with LiteX but perhaps I could help with it.
<_florent_>
Quarky93[m]: Sorry not yet, but I'm going to do it now, otherwise I'll never do it... :) I'll at least update the repository to have the updated version of the code
<Melkhior>
@gsomlo @_florent_ switched to the interrupt-based version of sdcard (turns out compiling the kernel was easy)
<Melkhior>
But boot is not reliable; often I get a lot of 'cmd 2' failed
<Melkhior>
very cold boot seems fine, but my PS/2 controllers (got 2 instance now, preparing for mouse) don't seem to like very cold boot
<Melkhior>
reset/reboot are mostly not working, "cmd 2 failed" :-(
<Melkhior>
short power-cycle doesn't help, long power-cycle seems needed ?!?
<_florent_>
Melkhior: when you say the boot is not reliable, it's the boot from the BIOS or the Linux boot?
<Melkhior>
Linux
<Melkhior>
_florent_ BIOS is always fine
<Melkhior>
root on the mmcblk0p2
<_florent_>
ok, I've not tested it yet personnaly
<Melkhior>
it may be that I have more source of interrupts than most and they are routed to core 0 at boot:
<_florent_>
so maybe you could try to just disable the SDCard interrupts in the .dts and see if it's behaving as before, if this, this could be related to changes in the linux driver
<Melkhior>
I'm running latest (as of early this morning) litex & linux/litex-rebase
<Melkhior>
will try the DTS change when I can
<Melkhior>
meanwhile it has booted with sd & kbd, sdcard seems to work fine once properly initialiazed
<Melkhior>
BTW, irqbalance succeeds (with a proper script) to move the IRQ to other cores:
<somlo>
Melkhior: I think if you just comment out any "interrupt[-parent]" lines in the mmc0 node, the linux driver will default to polling
<Melkhior>
@somlo OK will try that
<Melkhior>
Meanwhile once booted, not issue
<Melkhior>
recompiling Tk at -j4 from the sdcard :-)
<Melkhior>
what's 'cmd 2' ? any reason why it should fail after a reset ? (updated everything at once so it may not be the interrupt that is the issue...)
<somlo>
"all_send_cid" -- part of initialization
<somlo>
I typically get those when timing is a problem. Halving the sdclock usually makes them go away for me, and it's only still a problem on ecp5 with yosys/trellis/nextpnr, pretty solid on xilinx
<Melkhior>
@somlo mmm weird then, it was reliable before and I was running at 25 MHz, Artix-7 speed grade -2 & using vivado, so probably best case timing-wise
<Melkhior>
(and no negative slack at all)
<Melkhior>
will report when I have the time to test disabling interrupt
<Melkhior>
running at 25 MHz in Linux as well, no issue - it's purely a will boot/won't boot issue it seems
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<zyp>
_florent_, is there a reason all the examples in litex-boards that includes spi flash is using mode="1x"?
<_florent_>
zyp: IIRC it's only because I haven't spent the time to make it work in 4x on Fomu/Icebreaker
<zyp>
I just tried adding it to ecpix5, but both 1x and 4x modes are behaving weird, so I guess I should figure out how this is supposed to work first :)
<_florent_>
zyp: it should not be too complicated, but you need to instantiate the clock primitive and use the right dummy cycles value
<zyp>
all the examples used 8 for the dummy cycles -- after I increased it to 9 the 1x mode now looks reasonable
<zyp>
would it be the same number for 4x mode?
<_florent_>
The dummy cycles are related to the mode
<zyp>
in my case the flash is empty and all bytes reads cc in 4x mode
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<Melkhior>
@_florent_ somlo Seems I have no issue booting (cold or reset) without the interrupt for the sdcard in the DTS
<Melkhior>
geertu Do you know why Linux sees the cores as 'threads' rather than 'cores' ?
<Melkhior>
Thread(s) per core: 4
<Melkhior>
Core(s) per socket: 1
<Melkhior>
d-tlb-size = <8>;
<Melkhior>
d-tlb-sets = <8>;
<Melkhior>
i-tlb-size = <4>;
<Melkhior>
i-tlb-sets = <4>;
<Melkhior>
oups; first two lines are from lscpu
<Melkhior>
I've added in the DTS the specifier (above) for the TLB/MMU in each coreas it seemed to be a factor in the specifications, but Linux still says they are threads rather than cores
<Melkhior>
purely cosmetic issue of course, but still :-)
<Melkhior>
(I *think* some parameters I added in the VexRiscv cluster controls the TLB size/sets, hence the 8 for d-tlb, but I don't know if I can/how to measure the number of TLB reloads)
<Melkhior>
mmm seems this requires a 'cpu-map' node on Arm & RISC-V, it's not defined in the cpus/cpu nodes
<Quarky93[m]>
<_florent_ "Quarky93: This is finally done :"> Yay! thanks a lot 🙏
<_florent_>
I had to make some changes in LiteX to get it working since the HBM2 controller is adding debug probes on the JTAG chain 1, so I had to switch JTAG Bone to chain 2
<_florent_>
so you need to pull both LiteX (now allow selecting the JTAG chain for JTAGBone) and fk33_hbm2 repo
<Quarky93[m]>
ah ok cool
<Quarky93[m]>
Now to use this in the lamest way possible. as a giant fifo >.>
<_florent_>
In the design, I connected 4 AXI ports to the CPU, just to verify interconnection with the CPU, but this is not very efficient: 32-bit Wishbone --> 32-bit AXI-Lite --> 256-bit AXI-Lite --> AXI --> HBM
<_florent_>
When using the AXI ports directly with your logic and bursts, you should be able to get > 50Gbps per port with the current clocking (250MHz), but IIRC this can be increased to 450MHz
<_florent_>
A giant/fast FIFO is indeed a very nice use-case for this :)
<Quarky93[m]>
yep that's ok, I don't need too much bandwidth to the CPU. For my design CPU will only take one port, the rest will be spread across accelerators 🙂
<_florent_>
OK i see, thanks for pushing me a bit on this :) Interconnecting the AXI ports with your logic should not be too complicated even if you are not familiar with Migen/LiteX, but feel free to ask if you need help or provide feedback
<Quarky93[m]>
<_florent_ "OK i see, thanks for pushing me "> I will thanks! Basically I'm trying to have a PCIE endpoint whereby the host can load some initial data to HBM, then the RISCV will take it from there and orchestrate the accelerators to do stuff. RISCV will also attach to the ICAP to do dynamic reconfig to load different accelerators, thus the need for a giant FIFO to hide the latency :P
<Quarky93[m]>
It's nice that LiteX has almost all the infrastructure I need already, while being open source (apart from the xilinx IP)!
<Quarky93[m]>
<_florent_ "Quarky93: ok interesting, LitePC"> Yep, that's what initially got me interested in LiteX :D
<_florent_>
Now that we have all the interesting pieces, I'm indeed thinking about doing a project specific for accelerators where we could start with the Acorn CLE 215 to learn or low cost alternative and also support the BCU1525/FK33
<Quarky93[m]>
I wonder if the Acorn would be good for a compression/decompression algo
<_florent_>
I started prototyping something a year ago:
<Quarky93[m]>
it would be cool to be able to put it in your laptop (maybe with a heat sink bridge to the main heat sink)
<_florent_>
but some pieces were still missing or not very stable, now that we have almost everything thing (DDR4, PCIe, HBM2), it would make sense to spend some time on it
<Melkhior>
enough pins on those boards to get some hdmi out ? they look like they could be a good testbed for an open-source GPU if one ever gets complete enough...
<_florent_>
Quarky93[m]: the idea for the project is to rely on the core generators that are already present on LitePCIe, LiteDRAM, etc..
<Melkhior>
and GPUs are the original use case for HBM
<_florent_>
so you just create a configuration for each interface, generate the cores, and they would then be integrated along with the acceleration logic
<_florent_>
Melkhior: enough Pins on the FK33 our Acorn?
<_florent_>
our/or
<Quarky93[m]>
Unfortunately the FK33 does not have HDMI out. But the Jungle Cat modules can be mounted on a PCIE card with HDMI 2.0
<Melkhior>
@_florent_ any of them, really...
<_florent_>
The Acorn should have enough IOs
<Melkhior>
or even the VCU128
<_florent_>
but it would also be possible to just use the GTP from the PCIe connector for the 3 HDMI lanes + Clock :)
<_florent_>
this would work on the Acorn and FK33, and would even allow UHD/4K...
<_florent_>
this would just requires a small PCIe <--> HDMI adapter
<_florent_>
@Melkhior There is a 32-bit DDR3 which should gives around 20Gbps bandwidth with LiteDRAM
<_florent_>
the Acorn only has a 16-bit DDR3, so will be around 10Gbps
<_florent_>
Quarky93[m]:Kira SOMs indeed seems very interesting, but LiteX is less interesting than for regular FPGAs since most of the peripherals seem to be connected to the PS
<Quarky93[m]>
ahh right yea the RAM is on the PS side, as is the ethernet
<Melkhior>
A fullhd framebuffer at 60 Hz needs ~500 MB/s so 20Gbps should be fine
<Melkhior>
@_florent_ I'm guessing you connect the UART to the PCIe connector ? I don't see much external interface other than the PCIe and HDMI
<Melkhior>
(on the Mini 4K I meanà
<Melkhior>
)
<Melkhior>
... or jtag
<Melkhior>
is there jtag available on such a production board ?
<_florent_>
Melkhior: The UART is done over JTAG yes and the JTAG pinout is printed on the silkscreen... :)
<Melkhior>
ouch, you need soldering ? too bad:-( (I'm terrible at it)
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<_florent_>
The soldering is really easy
<_florent_>
Melkhior: In fact, it's possible to load a LiteX bitstream without any soldering or JTAG (just over PCIe with the default BlackMagic bistream + then with LitePCIe) but it's less convenient
<Melkhior>
@_florent_ but I'm guessing if you screw up the bitstream you need JTAG as a fallback ? And 'really easy' - terrible eyesight getting worse with age & and I was already bad at it when I was young and had two working eyes:-/ so I've given up trying
<Melkhior>
Seeedstudio PCBA & similar are a blessing, they do it all for me :-)
<_florent_>
Melkhior: Here it's only a matter of taking 2 x 5 pin row headers and soldering them on the PCB :)
<_florent_>
But this board was interesting for me since I also run some SDI designs on it, but it's maybe less interesting for others
<Melkhior>
@_florent_ how much memory does it have ?
<Melkhior>
The Wukong is nice as it's dirt-cheap, has hdmi/ethernet/sdcard onboard, so for a 'pc-like' litex soc it's great
<Melkhior>
but it only has 256 MiB :-(
<Melkhior>
And I've yet to dare hijack the VCU128 from the office to try LiteX on;-)
<Melkhior>
Speaking of 'pc-like' - X11 now running on fbdev, trying to borrow a PS/2 mouse as keyboard-only X11 isn't great :-)
<_florent_>
This one has 512MB
<_florent_>
the Acorn has 1GB
<Melkhior>
tempting :-)
<Melkhior>
thw
<Melkhior>
thx
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<_florent_>
I have plenty of Acorn CLE 215 that I bought to create projects with LiteX and share with other developers, happy to just sent you one if you want to play with it (and also to anyone contributing or willing to contribute to the project)
<Melkhior>
@_florent_ Thanks I'd love that ; but as i said - terrible at soldering:-) if there's some work needed to get peripherals (storage, network, ...) connected, you may want to favor someone more competent...
<Melkhior>
I remember seeing some sort of breakout board for it, but I don't remember if it was from you?
<_florent_>
zyp: yes is has been used on several designs, but mostly on 7-series I think
<zyp>
I've been probing the signals, so far everything looks fine but the flash is not responding and I don't understand why yet
<_florent_>
zyp: There is also LiteSPI (see arty target for an example), that is able to automatically calibrate the dummy cycles
<_florent_>
but the read latency seems higher with LiteSPI (It was a lot slower when doing XIP IIRC)
<zyp>
ah, I'll take a look at that later
<_florent_>
nickoe: it's not possible to load the bistream and use litex_server --jtag simultaneously no
<_florent_>
at least not as currently implemented
<nickoe>
_florent_: ok :/
<nickoe>
I was just hoping I overlooked something
<nickoe>
:D
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<_florent_>
gatecat: sorry, forgot to answer, thanks, yes it will be interesting to experiment with HBM2
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<nickoe>
_florent_: I am still trying to get my streaming thing working. Essetially reading data from SDRAM and popping it out with a slower rate. I am not sure how to LiteDRAMDMAReader efficently. Right now I am trying to take the data from LiteDRAMDMAReader and stuff it in to an AsyncFIFO to be able to pop out the data with a lower rate. But i am having issues with flow controlling it.
<nickoe>
Do you have any tips? ( no code attached to question as my current implemantion is messy and not really working... so I should probably start afresh...)
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