sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<cr1901_modern>
_florent_: Is there any particular reason that one CSR bank takes 256 bytes?
<cr1901_modern>
Real use case: I wanted to make a dual port SRAM. One side attaches directly to a softcore CPU, the other attaches as a CSR peripheral so I can dynamically reprogram the soft-core while collecting YM data
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<GitHub173>
[artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vsjlz
<cr1901_modern>
sb0: Wishbone memories of 8-bit data bus size cannot be created (which is what I need). Although you allow users to supply the data bus width and memory depth, you hardcoded the memory to expect 4 WB SEL signals. Is this a bug or intentional?
<sb0>
send a patch
<cr1901_modern>
Will do in a few minutes
<sb0>
do you have a misoc compatible board to test? this may cause an annoying regression on e.g. artiq-kc705
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<cr1901_modern>
I do not. I'll hold off/implement it manually in my source code for now if you wish/file a bug
<cr1901_modern>
(kc705 is waaaaaaaay out of my budget, btw, so chances are I will never own one)
<whitequark>
I will start by doing the transform itself, so in the worst case it will work, but would admit some incorrect programs
<whitequark>
I do think I can finish the type system part in time as well, though
<sb0>
and fixing unexpected bugs, I guess
<whitequark>
yes.
<sb0>
hmm. FUD works unreliably. which isn't totally unexpected considering there's no way to respect the setup/hold requirements with that hardware...
<sb0>
rjo, how do you ensure that the DDS always registers FUD despite the unfixable mess that the timing is? stretch it for 1.5 cycle?
<sb0>
and btw - ddstest doesn't test FUD, as another idiosyncrasy of this chip is the FTW registers read back the last *written* (not FUDed) value, unlike all other registers afaict
<sb0>
the ramp rate registers look like good candidates for testing FUD
<GitHub160>
[pythonparser] whitequark pushed 1 new commit to master: http://git.io/vGv3s
<GitHub160>
pythonparser/master 6d74932 whitequark: Include expanded_from in source.Range.__repr__.
<GitHub194>
[artiq] whitequark pushed 2 new commits to new-py2llvm: http://git.io/vGvW2
<GitHub194>
artiq/new-py2llvm 04bd242 whitequark: compiler.embedding: dedent kernel functions before parsing.
<GitHub194>
artiq/new-py2llvm c62b16d whitequark: compiler.embedding: support RPC functions as host attribute values.
<GitHub74>
[artiq] whitequark pushed 1 new commit to new-py2llvm: http://git.io/vGv8s
<GitHub74>
artiq/new-py2llvm f7c8625 whitequark: compiler.embedding: support calling methods via RPC as well.
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<GitHub59>
[artiq] fallen pushed 1 new commit to master: http://git.io/vGUQN
<GitHub59>
artiq/master 4a16ea1 Yann Sionneau: worker, scheduler: fix unit tests on Windows
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<travis-ci>
m-labs/artiq#445 (master - 4a16ea1 : Yann Sionneau): The build has errored.
<GitHub8>
artiq/master 4d84ec7 Yann Sionneau: update lx45 bscan bitstream url which wget could not fetch on some systems
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<rjo>
sb0: yes. I have debugged that unreliable fud here as well with raghu.
<rjo>
sb0: i would guess you can not read back anything that happens at the frontend. you will only ever look at the comminucation side registers and not at the high-speed side.
<rjo>
fud is one rtio-clk cycle right now, right? you can make it longer but the the fact that it is unreliable (while supposedly meeting setup/hold spec with externally clocked rtios) means that the problem is somewhere else and bigger.
<rjo>
making it longer would only move the problem from nothing happening at all to something happening one cycle too late.
<GitHub41>
[pythonparser] whitequark pushed 1 new commit to master: http://git.io/vGkjf
<GitHub41>
pythonparser/master 89d137f whitequark: algorithm.Visitor.visit: return a value if an array is passed as well.
<GitHub127>
[artiq] whitequark pushed 4 new commits to new-py2llvm: http://git.io/vGILD