00:24 <cr1901_modern> So... if I'm reading this document right http://www.xilinx.com/support/documentation/ip_documentation/dcm_module.pdf the way to use a DCM in Migen would be to simply create an instance with the correct inputs and outputs?

00:25 <cr1901_modern> I mean, Migen generates Verilog that can infer when to use multipliers and block RAM. Not so sure about DCMs

00:25 <cr1901_modern> Migen generates Verilog where ISE can infer*

09:49 <sb0> cr1901_modern, DCMs can never be inferred, migen or not

09:49 <sb0> so yes, create an instance. there are many examples in misoc.

10:42 <cr1901_modern> I know how to create an instance; just not as sure how to make ISE know "I want to use a DCM". Even the datasheet for the DCM says to use the GUI/only provides the inputs/outputs. The datasheet doesn't provide the actual module name.

10:42 <cr1901_modern> (I guess I could try DCM my_dcm()...)

10:47 <cr1901_modern> Huh, apparently "DCM" is in fact the module name. I guess I assumed it would've been something less obvious

11:31 <sb0_> rjo, why don't we see more QM experiments that use the gamma rays from positron/electron annihilation as entangled photon sources?

11:31 <sb0_> they are much cheaper and easier than BBO crystals, just use some radioactive sodium

11:32 <sb0_> and the photons can be detected with NaI scintillators, also easier and cheaper than SPADs or complicated PMT circuits, or perhaps even dirt cheap geiger tubes if you can cope with the inefficiency

11:36 <sb0_> maybe beam-splitters are hard?

11:55 <sb0_> hackaday is getting good these days. https://hackaday.io/project/1376-pyppm-a-proton-precession-magnetometer-for-all

15:39 <sb0> _florent_, is k7ddrphy usable for any other memory than ddr3?

15:40 <_florent_> probably not since we are assuming burst length of 8

15:40 <_florent_> ah maybe DDR2 supports that

15:41 <sb0> well, you can do burst length 8 on all DRAMs

15:41 <sb0> no?

15:41 <_florent_> yes probably in fact...

15:42 <_florent_> but i've only used k7ddrphy on ddr3

15:42 <sb0> ok. so let me just hardcode DDR3 memtype in the PHY...

15:42 <sb0> so as not to give the false impression that it is supposed to work with something else

15:43 <_florent_> ok yes

15:43 <sb0> (it probably works with no or little modifications, but better be pessimistic about this sort of thing...)

15:44 <_florent_> yes, we'll change that if needed

15:45 <_florent_> and I'm not sure we are going to use others memories with 7-series

15:46 <sb0> 7-series are still slow enough that DDR2 maxes out their IO bandwidth, no?

15:47 <sb0> and DDR2 has less latency than DDR3 ...

15:52 <sb0> ah, no, the -3 kintex speed grade is faster than ddr2.

15:55 <sb0> and ultrascale maxes out at 2.4GT/s while commonly available DDR3 is 2.1GT/s

15:56 <sb0> so DDR4 can have slightly more bandwidth on those

15:58 <sb0> ultrascale is pricy ...

16:01 <sb0> #*?=)"(§!! "effective LEs"

16:03 <sb0> anyway. they're huge too, with the smallest device at 145K LUTs...

16:05 <sb0> how do you use all this space oO

16:06 <sb0> I'm sure vivado takes an eternity compiling for them

16:07 <sb0> not to mention how many gigabytes, if not terabytes, of RAM it probably uses ...

16:19 <sb0> _florent_, at what frequency are you running the DDR3 on S6?

16:20 <_florent_> not high for now, 200MHz so DDR400

16:21 <sb0> does this still lock the DLL?

16:32 <sb0> micron datasheets say the clock period must be less than 3.3ns

16:34 <sb0> and less than 8ns with the DLL disabled

16:34 <sb0> are you disabling the DLL?

16:37 <sb0> actually, it seems with the DLL disabled you can operate DDR3 at arbitrarily low frequencies if it wasn't for the refresh... maybe something that can come useful in heavy-handed PHY debugging sessions

16:39 <_florent_> yes that's out of spec, but dll is locking

16:40 <_florent_> I'll try to increase freq a little bit to be closer to 3.3ns

16:42 <sb0> s/less than 8ns/more than 8ns

19:02 <rjo> sb0: same reason we don't actually use cats: they might be easy to make and to detect but there are very limited optics, manipulation, and mapping methods. making good entangled pairs is a valid undergraduate experiment (or something to impress hackaday or a hackerspace) but using it to make something new is harder.

19:03 <_florent_> affordable artix7 board: http://www.em.avnet.com/en-us/design/drc/Pages/Artix-7-35T-FPGA-Evaluation-Kit.aspx?cmp=na-aes3-pr-201509

19:04 <_florent_> can be interesting for ARTIQ...

19:09 <cr1901_modern> Yea, I was going to bring that dev board up. Idk how Artix compares to Spartan 6 in terms of size/perf (haven't checked)

19:14 <_florent_> Artix family is easier to work with than Spartan6 family

19:14 <_florent_> and vivado is very fast compared to ISE

19:15 <cr1901_modern> Does vivado support Spartan 3?

19:15 <cr1901_modern> I need it for my current dev board

19:16 <_florent_> no

19:16 <_florent_> only 7series

19:17 <_florent_> you should invest in this little board and port misoc to it, would be a good exercice :)

19:19 <cr1901_modern> Well it is a cute board, and I do have the money (though I need to save it)...

19:22 <cr1901_modern> Oh right, I need to actually buy a JTAG cable unless I can figure out how to use rjo's OpenOCD patch