sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0> whitequark, the extra OSERDESE2 are for the command and address pins
<sb0> yeah, i2c should be at something like 5kHz
<whitequark> doesn't it usually run at 100khz?
<sb0> "update value" registers are necessary to make reads larger than the bus atomic
<sb0> you could try at 100kHz. but 5kHz is fine, there is no minimum frequency
<cr1901_modern> Who wrote the bitbang impl? I assume it just wasn't worth the effort to make a core?
<sb0> the use case of the current i2c code is to program a few registers in a couple chip at device startup
<sb0> so i did not try to optimize anything for speed
<sb0> and i wrote that bitbang implementation, 11 years ago. original use case was to control a LCD module on a modded wifi card.
<cr1901_modern> sb0: It's pretty good and concise, as far as bitbanging impls go.
<whitequark> sb0: so what clock frequency will it be?
<sb0> it doesn't matter, does it? do you need to transfer data fast?
<whitequark> no, not i2c, input frequency for dejitter
<sb0> oh
<sb0> 125MHz in and out
<sb0> I thought that was in my email already
<whitequark> oh
<whitequark> yeah, it was
<sb0> can this thing control the delay/phase between input and output?
<whitequark> yes
<whitequark> in some way
<whitequark> INDEPENDENTSKEW1.
<whitequark> 8 bit field that represents a twos complement of the phase offset in
<whitequark> terms of clocks from the high speed output divider. Default = 0.
<whitequark> looks like it doesn't have a lot of resolution...
<whitequark> well, no, a lot of range.
<sb0> okay, so what resolution and range will we get with the settings you are programming right now?
<whitequark> don't know yet; I'm figuring out their software right now
<whitequark> okay, so you have phase offset resolution of 1ns and range of 8 bit
<whitequark> i.e. from -128ns to +127ns
<sb0> ok, so it's full phase control at 125MHz
<whitequark> I suspect that's exactly what their calculator is aiming for
<whitequark> i.e. it set up the divisors and multipliers so you'd get that
<whitequark> hmmm, that's weird
<whitequark> it acks transfers but the part# i read from it is 0xffff
<whitequark> oh, i2c reads are just broken
<whitequark> oh. no. no they aren't
<whitequark> sb0: are there accessible testpoints for i2c or something?
<whitequark> or reset, I guess?
<whitequark> hm, this should be in a doc somewhere
<sb0> did you set the i2c addresses right?
<whitequark> yes
<whitequark> and in fact if I fudge address, I get an abort on failed ack, as expected
<whitequark> there doesn't appear to be any power gating, and I wait for 20ms after reset (DS requires 10ms)
<whitequark> tried waiting for 1s, no difference anyway
<whitequark> if I invert reset polarity, then I don't get acks
<whitequark> so clearly it is the si5324 that sends the ack
<whitequark> oh, hm, maybe I'm not poking it right
<whitequark> the DS doesn't actually say anywhere how you are supposed to write or read its registers
<whitequark> hm, no, I am poking it right
<whitequark> oh
<whitequark> sb0: your i2c bitbang code doesn't handle repeated starts correctly
<sb0> possibly, i didn't look into implementing that
<whitequark> sb0: what sort of input does the FPGA "MGT REFCLK INPUT" expect?
<whitequark> the datasheet says N/A
<whitequark> and si5324 has a few choices, like CMOS, LVDS, etc
<sb0> it's certainly a differential one
<sb0> the transceiver data is CML
<sb0> I don't know about clocks
<whitequark> do you need clock alarms?
<sb0> what's that?
<sb0> PLL unlocked signals?
<whitequark> it can monitor clock for deviation from its proper frequency
<whitequark> and then it can synthesize it from nothing in "digital hold", even ignoring some time just before the failure
<sb0> nah, I can get those from the fpga transceiver
<sb0> those *might* be useful to debug the transceiver if it starts acting funny, but there may be simpler means anyway
<sb0> clock input will take LVDS or LVPECL
<whitequark> ok, LVPECL is the default
<sb0> LVPECL requires additional resistors which I think are not on the KC705 (see schematics)
<sb0> so I think you should switch it to LVDS
<whitequark> oh
<sb0> how do you want to measure the clock?
<whitequark> scope?
<sb0> got access to those pins?
<whitequark> no, but they can be routed within the FPGA
<whitequark> to USER SMA et
<whitequark> etc
<sb0> yes. but routing them through the FPGA probably requires this IBUFDS_GTE2 buffer, can it drive anything else than the transceiver's clock input?
<whitequark> mhm
<sb0> does vivado yell at you if you put a IBUFDS instead on those pins, or if you cascade a IBUFDS_GTE2 with a BUFG?
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<GitHub117> [si5324_test] whitequark pushed 1 new commit to master: https://github.com/m-labs/si5324_test/commit/d4b2dcab82d1fc922e882043280a15953e188298
<GitHub117> si5324_test/master d4b2dca whitequark: Add Si5324 initialization for 125MHz.
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<whitequark> it does not seem to mind
<whitequark> sb0: where do I take dirty clock?
<whitequark> just generate it with a PLL?
<sb0> yeah, for example
<whitequark> oh
<whitequark> self.cd_sys.clk is already at 125MHz
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<GitHub50> [si5324_test] whitequark pushed 1 new commit to master: https://github.com/m-labs/si5324_test/commit/d029c166dc69f2b9966ad54c59ee8cc1d7aa5cff
<GitHub50> si5324_test/master d029c16 whitequark: Add clock routing.
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<whitequark> *facedesk*
<whitequark> spent 20 minutes wondering why there's no clock. answer: because I forgot to add the submodule with routing
<whitequark> sb0: ok, yeah, vivado doens't like this arrangement of clocks
<whitequark> ibufds_gte2...
<sb0> what did you connect to get this error?
<sb0> for the output, you need to use OBUFDS, maybe with ODDR (though it may be routable directly on 7-series, not sure)
<whitequark> IBUFDS and OBUF
<whitequark> oh
<sb0> what are you connecting exactly?
<sb0> for the output, try OBUFDS i_I=ClockSignal() o_O=clkout_p o_OB=clkout_n
<sb0> input - I don't really know
<whitequark> si5324_clkout.p, i_IB=si5324_clkout.n to user_sma_gpio_p
<sb0> just that?
<whitequark> yeah
<sb0> okay, and sma_gpio_p is not using a differential standard?
<whitequark> LVCMOS33, so I think not
<sb0> ok
<sb0> hmm
<whitequark> hm, I added an IBUF
<whitequark> IBUFDS_GTE2 and a BUFG and now I have an iostandard mismatch
<sb0> added an IBUF?
<whitequark> between si5324_rst_n and user_sma_gpio_p
<whitequark> added an IBUFDS_GTE2.
<sb0> IBUF will never work, it's for non-differential inputs
<whitequark> I didn't add an IBUF, I pressed enter instead of _
<whitequark> I understand that.
<sb0> ok so you are doing IBUFDS_GTE2 -> BUFG -> single-ended output?
<sb0> what is the exact error message?
<sb0> what is si5324_int?
<whitequark> interrupt out
<sb0> shouldn't si5324_int and si5324_rst_n be LVCMOS33?
<sb0> instead of 25
<whitequark> I took LVCMOS25 from their doc
<whitequark> it lists constraints in appendix
<whitequark> and actually they list user_sma_gpio_[pn] as LVCMOS25
<sb0> bah, what is the VCCO of the bank on the kc705 schematics?
<whitequark> 2.5V(default)
<whitequark> it's VADJ_FPGA
<whitequark> shall I fix the iostandard of user_gpio?
<GitHub70> [migen] whitequark pushed 1 new commit to master: https://git.io/voZis
<GitHub70> migen/master 5630b7c whitequark: platforms/kc705: use correct IO voltage for user_sma_gpio_{p,n}....
<bb-m-labs> build #77 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/77
<bb-m-labs> build #110 of misoc is complete: Exception [exception interrupted] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/110
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<whitequark> okay, I get clock now, but not PLL lock... hm
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<GitHub32> si5324_test/master f2964d9 whitequark: Actually use routed clock.
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<GitHub32> [si5324_test] whitequark pushed 1 new commit to master: https://github.com/m-labs/si5324_test/commit/f2964d9784aee6eb11872ebd116f0e2b32d14307
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<sb0> _florent_, larsc: in regular data transfer applications (pcie, sdi, ...), what is the use case for clocking the transceiver TX with the cleaned-up RX CDR clock?
<sb0> it seems to me that it's simpler to just use the local oscillator to clock TX - no Si5324 chip, no complicated transceiver settings
<sb0> well, maybe for sdi you want genlock
<sb0> but for pcie it makes no sense at all afaict
<larsc> I have no idea
<larsc> it might make sense if both sides use a different reference clock
<sb0> if they use a different reference clock, RX won't work either
<sb0> CDR can only compensate for a small frequency difference
<larsc> different in the sense of same frequency but different crystal so you'll have a slight offset
<sb0> yes, but there is already the clock correction mechanism that can deal with that by inserting or removing comma characters
<sb0> you just have to make sure that your data stream regularly contains series of at least two commas
<sb0> and you need at least a regular one for RX alignment
<sb0> already
<larsc> but maybe having the same frequency makes it more reliable or whatever
<larsc> who recommends such a setup, Xilinx?
<sb0> I don't see why clock correction would be unreliable
<sb0> haven't found docs on this yet, I just see designs seemingly doing that
<larsc> ok, maybe just copy&paste than
<sb0> possibly
<sb0> bbl
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<GitHub36> [artiq] sbourdeauducq pushed 5 new commits to master: https://git.io/vonew
<GitHub36> artiq/master ca9724f Sebastien Bourdeauducq: doc: add core device comms details
<GitHub36> artiq/master eb359ce Sebastien Bourdeauducq: Revert "master/worker: pause/resume devices"...
<GitHub36> artiq/master 4472419 Sebastien Bourdeauducq: Revert "master/worker_db: add pause_devices and resume_devices"...
<GitHub86> [artiq] sbourdeauducq pushed 2 new commits to release-1: https://git.io/vone6
<GitHub86> artiq/release-1 7e9fa3a Sebastien Bourdeauducq: doc: add core device comms details
<GitHub86> artiq/release-1 d3f092c Sebastien Bourdeauducq: doc: add warning about pipistrello current draw
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<bb-m-labs> build #465 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/465
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<bb-m-labs> build #209 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/209
<bb-m-labs> build #735 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/735
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<whitequark> hm
<whitequark> is there possibly something about OBUFDS that divides the clock by half?
<whitequark> hmm, no
<whitequark> hum, weird, I can't get the PLL locked with the values their program gives
<whitequark> but I can fudge it a bit and then it locks onto something
<whitequark> oh *facepalm*
<whitequark> the logical register values do not map 1:1 to the binary register values
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<DocScrutinizer05> hi!
<whitequark> hi
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<GitHub193> [si5324_test] whitequark pushed 1 new commit to master: https://github.com/m-labs/si5324_test/commit/2d1de1554dae6b66910fc23329448bd9d2757902
<GitHub193> si5324_test/master 2d1de15 whitequark: Fix values written to registers; add skew control API.
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<whitequark> sb0: ok, that's all done
<DocScrutinizer05> whitequark: wasn't aware it was m-labs (formerly known as milkymist) you're working for
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<GitHub15> [artiq] sbourdeauducq pushed 3 new commits to master: https://git.io/vonnS
<GitHub15> artiq/master 60d8e30 Sebastien Bourdeauducq: scanwidget: value may be None
<GitHub15> artiq/master 765e3f0 Sebastien Bourdeauducq: gui/entries/_RangeScan: set range before setting value. Fixes clamping to 99.99
<GitHub15> artiq/master 3b63c39 Sebastien Bourdeauducq: gui/scanwidget: use -inf/inf to represent absence of boundaries (consistently with QDoubleSpinbox)
<GitHub188> [artiq] sbourdeauducq pushed 3 new commits to release-1: https://git.io/vonnN
<GitHub188> artiq/release-1 9dcd43f Sebastien Bourdeauducq: gui/scanwidget: use -inf/inf to represent absence of boundaries (consistently with QDoubleSpinbox)
<GitHub188> artiq/release-1 1faac10 Sebastien Bourdeauducq: scanwidget: value may be None
<GitHub188> artiq/release-1 ddd1c12 Sebastien Bourdeauducq: gui/entries/_RangeScan: set range before setting value. Fixes clamping to 99.99
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<bb-m-labs> build #466 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/466
<bb-m-labs> build #210 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/210
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<bb-m-labs> build #736 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/736
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