sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0> whitequark, there have been many lwip commits since the version we're using, perhaps that keepalive bug has been fixed - and if not, it seems lwip is pretty actively developed, so they may have an idea how to fix it
<sb0> rjo, there have been several PPP VJ compression commits too
<whitequark> sb0: OK, I will look at those too
<sb0> the only reason we're using an old lwip is PPP regressions
<sb0> and I'd argue that fixing the ethernet bugs is more important than PPP anyway
<sb0> whitequark, what are those new llvmlite branches for?
<sb0> linker?
<whitequark> sb0: this is an extremely old patchset that I made for llvmlite upstream
<whitequark> and they wanted to see it updated for months
<whitequark> the linker changes are for a different linker, that is irrelevant to us
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<GitHub90> [artiq] sbourdeauducq pushed 1 new commit to master: https://git.io/voz8l
<GitHub90> artiq/master 9a1cad5 Sebastien Bourdeauducq: dashboard: basic dataset editing capabilities
<GitHub193> [artiq] sbourdeauducq pushed 1 new commit to release-1: https://git.io/voz8V
<GitHub193> artiq/release-1 770dda6 whitequark: transforms.inferencer: allow variable as type of `n` in `[]*n`....
<sb0> whitequark, can you merge c0e42bbfc889fd28138f000e2e8a5a1f53fcb46b into release-1? there's a conflict.
<whitequark> moment
<whitequark> merge or cherry-pick?
<sb0> cherry-pick
<GitHub25> [artiq] whitequark pushed 1 new commit to release-1: https://git.io/voz85
<GitHub25> artiq/release-1 cc28b59 whitequark: compiler.embedding: always do one final inference pass....
<bb-m-labs> build #474 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/474
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<rjo> yes. i had tested them a while ago. they break things.
<bb-m-labs> build #218 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/218
<rjo> maybe it's gotten better now. but everything until a few months ago is definitely broken.
<bb-m-labs> build #744 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/744
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<Marcelos> Hello. I'm looking for a FPGA platform to implement a video processing algorithm. Do you think the Mixxeo could be a good choice?
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<mumptai> is there an example for an testbench that does read/write access to some CSR registers?
<sb0> Marcelos, look at numato opsis
<Marcelos> sb0: i did. it looks interesting, but i need some vhdl reference design, it doesn't seem to have
<mumptai> Marcelos, is VHDL really required?
<Marcelos> yes, i want to integrate in a board a design that i have already developed in vhdl but only tested in simulations
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<mumptai> i don't know much about the opsis, but it looks like some spartan6 board with hdmi/usb/ethernet and sdram, i wouldn't expect any unusual surprises. the interfaces are just not trivial to get up and running
<mumptai> (the "just" might be a vast understatement)
<mumptai> what about using mixed-language simulation and synthesis?
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