<sb0>
whitequark, you really don't like the misoc csr generator?
<sb0>
it would have prevented all the problems you had with the wishbone interface
<sb0>
you are decoding on all bits now, this uses too many resources and timing slack, and more importantly will fail if the core is not mapped to address 0
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<whitequark>
I never figured out how the csr generator works
<whitequark>
maybe if it was documented...
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<cr1901_modern>
whitequark: The CSR generator will check all attributes and submodules of the passed-in Migen module and look for a "get_csrs" method in all the attributes. The get_csrs method provided by "AutoCSR" will examine all the attributes of any instantiated subclass of AutoCSR, and look for matches to CSRStorage and CSRStatus. Any matches it finds are added to a list (or tuple? I forget) of subclasses of CSR, which has enough informatio
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<GitHub144>
[migen] sbourdeauducq pushed 1 new commit to master: https://git.io/v6JFe
<whitequark>
sb0: so is there any documentation on writing migen testbenches?
<whitequark>
this clever coroutine crap breaks and I've no idea why
<whitequark>
oh, forgotten `yield from`
<whitequark>
I guess I should write said documentation once I'm done...
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<sb0>
whitequark, excellent initiativw
<sb0>
*initiative
<whitequark>
so
<whitequark>
yield dut.i2c.sda_i.eq(False)
<whitequark>
print((yield dut.i2c.sda_i))
<whitequark>
yield dut.i2c.sda_i.eq(True)
<whitequark>
print((yield dut.i2c.sda_i))
<whitequark>
this prints 0 and 0
<whitequark>
why?
<sb0>
reads happen immediately before the current clock edge, writes happen immediately after the edge
<whitequark>
yield dut.i2c.sda_i.eq(True)
<whitequark>
yield
<whitequark>
print((yield dut.i2c.sda_i))
<whitequark>
still 0
<sb0>
nothing else driving it?
<whitequark>
hm
<whitequark>
oh, the tristates...
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<whitequark>
good call. there were two bugs in reads
<sb0>
okay, please commit everything to the drtio_transceiver_test repos
<whitequark>
unable to
<whitequark>
oh
<sb0>
thanks!
<sb0>
ah you have deleted the C stuff
<whitequark>
yeah, what's wrong with that?
<whitequark>
you can check out an earlier commit if you want it
<sb0>
whitequark, do we need to send a reset pulse to the si5324 or is it fine without?
<sb0>
I suppose we at least need to drive rst_n?
<sb0>
also, 1) if (for whatever reason) you generate a reset in one clock domain and register it into another domain, you need AsyncResetSynchronizer
<sb0>
resets do need to be synchronized, otherwise there is an uncertainty on the clock cycle when the reset is removed, which can put the design into an inconsistent state
<whitequark>
yeah, I know that
<sb0>
2) manual BUFG insertion on reset signals is not required
<whitequark>
did I not do this correctly somewhere?
<sb0>
yes, in si5324_test, clk200 to cd_sys.rst
<whitequark>
ohh
<whitequark>
oh yeah
<sb0>
nevermind, I'll just add the si5234 reset pulse
<whitequark>
the reset pin has an internal pull-up
<whitequark>
also, it doesn't look like reset is necessary
<sb0>
good. recovers on its own from broken clocks, doesn't require resets - looks like a properly designed chip for once
<whitequark>
silabs makes good chisp
<whitequark>
cp2102 is an excellent USB-Serial converter, way nicer than the crap FTDI does
<sb0>
yup, ftdi is garbage. they should mark all registers as "reserved", and just give blobs that happen to work, because pretty much any settings not in a reference design tickle silicon bug
<sb0>
it can be totally random, e.g. a GPIO will stop to work if you change the JTAG frequency
<whitequark>
and they're expensive as hell too
<sb0>
whitequark, also generally you do not need manual OBUFs
<sb0>
for most signals, if you just take them out of the chip, Vivado will insert the required OBUF automatically
<whitequark>
ah, I think I did that for symmetry with OBUFDS
<sb0>
ok. yes, differential signals need explicit buffers
<sb0>
okay, clock cleanup is working great with the transceiver
<GitHub42>
[migen] whitequark pushed 1 new commit to master: https://git.io/v6Ukb
<GitHub42>
migen/master 9f9b0d0 whitequark: doc: explain how simulation works.
<sb0>
hm, yes, and it requires decorating everything
<whitequark>
can't you define a __del__ on any function?
<sb0>
or use "async def" and a global wrapper; if we mess with the global wrapper it will cause trouble if a test bench also uses asyncio for some reason
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<sb0>
okay, everything looks good on the scope as well re. si5324; also works with the TTL demo