sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<bb-m-labs> build #188 of conda-lin64 is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/conda-lin64/builds/188
<GitHub99> [conda-recipes] whitequark pushed 1 new commit to master: https://github.com/m-labs/conda-recipes/commit/bf9a2d185e29dbdf3d83dda11600087a397f5481
<GitHub99> conda-recipes/master bf9a2d1 whitequark: llvm-or1k: use host cmake instead of conda's 3.4 (too old).
<whitequark> bb-m-labs: force build --props=package=llvm-or1k conda-lin64
<bb-m-labs> build #189 forced
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #151 of conda-win32 is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/conda-win32/builds/151
<bb-m-labs> build #189 of conda-lin64 is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/conda-lin64/builds/189
<whitequark> hm, what the heck
<GitHub196> [conda-recipes] whitequark force-pushed master from bf9a2d1 to 73ead27: https://github.com/m-labs/conda-recipes/commits/master
<whitequark> sb0: oh excellent, 3.9 has some new optimizations that perfectly fit the semantics needed by ARTIQ
<whitequark> so I think we can optimize slightly more aggressively
<bb-m-labs> build #142 of conda-win64 is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/conda-win64/builds/142
<bb-m-labs> build #67 of conda-all is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/conda-all/builds/67
<GitHub144> [conda-recipes] whitequark pushed 1 new commit to master: https://github.com/m-labs/conda-recipes/commit/a92185bb19c342178ce9d866297600ddb95ea4f1
<GitHub144> conda-recipes/master a92185b whitequark: llvm-or1k: require cmake 3.4.*.
<whitequark> bb-m-labs: force build --props=package=llvm-or1k conda-lin64
<bb-m-labs> build #190 forced
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #190 of conda-lin64 is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/conda-lin64/builds/190
<GitHub60> [conda-recipes] whitequark force-pushed master from a92185b to bf9a2d1: https://github.com/m-labs/conda-recipes/commits/master
<GitHub60> conda-recipes/master bf9a2d1 whitequark: llvm-or1k: use host cmake instead of conda's 3.4 (too old).
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<whitequark> bb-m-labs: force build --props=package=llvm-or1k conda-lin64
<bb-m-labs> build #191 forced
<bb-m-labs> I'll give a shout when the build finishes
<whitequark> hm, rust didn't add a 3.9 *requirement*, oops
<whitequark> ah well, i already ported everything to 3.9, could as well go along with it
<whitequark> especially given those optimizations
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<bb-m-labs> build #191 of conda-lin64 is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/conda-lin64/builds/191
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<whitequark> bb-m-labs: force build --props=package=llvmlite-artiq conda-all
<bb-m-labs> build #68 forced
<bb-m-labs> I'll give a shout when the build finishes
<GitHub14> [conda-recipes] whitequark pushed 1 new commit to master: https://github.com/m-labs/conda-recipes/commit/1fb70ca1d4fef2c584b362286036094d0ba1ce02
<GitHub14> conda-recipes/master 1fb70ca whitequark: llvmlite-artiq: update for LLVM 3.9.
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<bb-m-labs> build #192 of conda-lin64 is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/conda-lin64/builds/192
<bb-m-labs> build #152 of conda-win32 is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/conda-win32/builds/152
<bb-m-labs> build #143 of conda-win64 is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/conda-win64/builds/143
<bb-m-labs> build #68 of conda-all is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/conda-all/builds/68
<GitHub199> [artiq] whitequark pushed 1 new commit to master: https://git.io/v6uce
<GitHub199> artiq/master 895b25b whitequark: Update for LLVM 3.9.
<bb-m-labs> build #870 of artiq is complete: Failure [failed lit_test] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/870 blamelist: whitequark <whitequark@whitequark.org>
<GitHub191> [artiq] whitequark force-pushed master from 895b25b to 3aa7b99: https://git.io/vYgPK
<GitHub191> artiq/master 3aa7b99 whitequark: Update for LLVM 3.9.
<bb-m-labs> build #594 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/594
<bb-m-labs> build #871 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/871 blamelist: whitequark <whitequark@whitequark.org>
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<whitequark> bb-m-labs: force build artiq
<bb-m-labs> build forced [ETA 27m17s]
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #595 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/595
<bb-m-labs> build #872 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/872
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<whitequark> oh well. test_pulse_rate_dds regressed by 100ns
<GitHub166> [artiq] whitequark pushed 1 new commit to master: https://git.io/v6uWZ
<GitHub166> artiq/master 5f59758 whitequark: Revert "Update for LLVM 3.9."...
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<bb-m-labs> build #596 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/596
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<bb-m-labs> build #307 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/307
<bb-m-labs> build #873 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/873
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<key2> sb0: if I have a io pin that I want to output the same as the clk, how do I write that in migen ?
<sb0> comb += io.eq(ClockSignal())
<sb0> some fpga e.g spartan6 need special tricks.
<key2> ah such as ?
<sb0> on s6 global clock nets are not routable to ios. the trick is to use ODDR2 with fixed data inputs.
<whitequark> why can't the synthesizer infer that itself?
<whitequark> or PAR
<whitequark> whatever works
<key2> and that works as well if I use a PLL ? basically a SDCard could go up to ~104 Mhz. so I was giving that out of a PLL as the clock domain
<key2> sb0: how would you do this trick if you had DDR2 pins driven by this clock ?
<sb0> whitequark, no idea. that's just how it's done (and it's one of the least annoying s6 ise clock problems)
<sb0> PLL outputs are routable to global clock nets, yes. there are design flaws in s6 clocking, but not _that_ big.
<sb0> what is a "ddr2 pin" and how does it relate to clocking?
<key2> sb0: it means that on recent SDCard, the 4bits data lines are DDR
<key2> so there is data on rising and falling edge of the clk
<key2> if I understand your solution, you are telling me to ODDR on the clk line, in order to generate a pattern that would look the same as the ClockSignal
<sb0> "ODDR on the clock like" is equivalent to comb += io.eq(ClockSignal()) and all it does is work around the s6 routing limitations and the ISE idiocy
<sb0> for fast SD you have to do clock speed changes, no?
<key2> self.specials += DDROutput(1, ClockSignal() , 0 , my_oudput_clock)
<key2> ?
<key2> sb0: no you are not forced, in fact you could even ignore the low speed at the beginning
<key2> old sdcard required 74 ticks at 400Khz clocking
<key2> how would I create this output from ddr ? self.specials += DDROutput(1, 1, 0 , my_oudput_clock) ?
<key2> this way ?
<key2> oops
<key2> self.specials += DDROutput(1, 0 , my_oudput_clock)
<key2> ?
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<larsc> can you directly connect clocks to outputs on series7?
<sb0> yes
<sb0> or at least, vivado does it without complaining
<sb0> this also worked on other fpgas, like virtex4
<larsc> hm, let me try it and see how the routing looks like
<larsc> or whether it impliciitly inserts a ODDR
<key2> why does TB freez sometimes ?
<key2> sb0: I have this very simple example but I wonder why the TB doesnt go further than 2 steps http://pastebin.com/aLceknpZ
<key2> can you see something that looks wrong ?
<sb0> yes, you have signal.eq(~signal) in comb
<larsc> hm, ok looks like you can directly route a global clock net to a output pin, local clock nets (BUFIO, BUFR) dont work
<larsc> the problem of course is that there will be a routing depending skew between clock and data
<larsc> whereas if you u
<larsc> use ODDR all outputs are update at the same time
<larsc> and then you can use ODEALY to get predictable skew
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<larsc> in my tests going from the BUFG to the OBUF is about 1ns slower than going from the BUFG to the clock input of the ODDR
<larsc> but of course the ODDR itself also adds a bit of delay
<key2> sb0: thx
<key2> did you find it by just reading my code or you tried it to find out ?
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<sb0> reading
<sb0> doesn't the ODDR have a OBUF as its output?
<sb0> and the skew on a global clock net is supposed to be small
<larsc> the difference is less than a 1ns
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<key2> in endpoints, is it always the source that gives the info from layout to the sink ? or could the sink send something on its Records to the sournce when Acking ?
<sb0> only source to sink
<key2> ok
<sb0> I'm reading Einstein's 1917 paper and he writes that the probability dW of spontaneous emission during the time dt is dW=Adt
<sb0> there's probably some formalism here I don't understand, because if you integrate this you get W=At, which goes over 1 for large values of t
<cr1901> isn't dW supposed to represent a *change* in probability anyway?
<sb0> how do you get the exponential law from this?
<sb0> yes, and?
<cr1901> What I'm asking is: Is a differential probability meaningful physical value? They appear in all prob density functions, but I'm not aware that taking the value of a PDF at a single point is a meaningful value.
<cr1901> I'm getting hung up on how he would've derived this
<sb0> the equation that gets you exponential law is dW=WAdt, not dW=Adt
<sb0> maybe W is not a probability.
<cr1901> Right... any exponential function is of the form f' = kf
<cr1901> I would have to read the paper. And also brush up on my probability.
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<larsc> doesn't that just say that the probability at any point in time is A?
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<cr1901> larsc: then why didn't he use "t" instead of dt?
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<larsc> cr1901: what do you mean?
<cr1901> larsc: Nevermind for now
<larsc> it's a diff equation if you solve it for a function of W' you get W'(t) = A, I think
<larsc> and W' was defined as the probability
<larsc> but I think I'm missing something somewhee
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