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<key2>
sb0: if I have a io pin that I want to output the same as the clk, how do I write that in migen ?
<sb0>
comb += io.eq(ClockSignal())
<sb0>
some fpga e.g spartan6 need special tricks.
<key2>
ah such as ?
<sb0>
on s6 global clock nets are not routable to ios. the trick is to use ODDR2 with fixed data inputs.
<whitequark>
why can't the synthesizer infer that itself?
<whitequark>
or PAR
<whitequark>
whatever works
<key2>
and that works as well if I use a PLL ? basically a SDCard could go up to ~104 Mhz. so I was giving that out of a PLL as the clock domain
<key2>
sb0: how would you do this trick if you had DDR2 pins driven by this clock ?
<sb0>
whitequark, no idea. that's just how it's done (and it's one of the least annoying s6 ise clock problems)
<sb0>
PLL outputs are routable to global clock nets, yes. there are design flaws in s6 clocking, but not _that_ big.
<sb0>
what is a "ddr2 pin" and how does it relate to clocking?
<key2>
sb0: it means that on recent SDCard, the 4bits data lines are DDR
<key2>
so there is data on rising and falling edge of the clk
<key2>
if I understand your solution, you are telling me to ODDR on the clk line, in order to generate a pattern that would look the same as the ClockSignal
<sb0>
"ODDR on the clock like" is equivalent to comb += io.eq(ClockSignal()) and all it does is work around the s6 routing limitations and the ISE idiocy
<sb0>
for fast SD you have to do clock speed changes, no?
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<larsc>
can you directly connect clocks to outputs on series7?
<sb0>
yes
<sb0>
or at least, vivado does it without complaining
<sb0>
this also worked on other fpgas, like virtex4
<larsc>
hm, let me try it and see how the routing looks like
<larsc>
or whether it impliciitly inserts a ODDR
<key2>
why does TB freez sometimes ?
<key2>
sb0: I have this very simple example but I wonder why the TB doesnt go further than 2 steps http://pastebin.com/aLceknpZ
<key2>
can you see something that looks wrong ?
<sb0>
yes, you have signal.eq(~signal) in comb
<larsc>
hm, ok looks like you can directly route a global clock net to a output pin, local clock nets (BUFIO, BUFR) dont work
<larsc>
the problem of course is that there will be a routing depending skew between clock and data
<larsc>
whereas if you u
<larsc>
use ODDR all outputs are update at the same time
<larsc>
and then you can use ODEALY to get predictable skew
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<larsc>
in my tests going from the BUFG to the OBUF is about 1ns slower than going from the BUFG to the clock input of the ODDR
<larsc>
but of course the ODDR itself also adds a bit of delay
<key2>
sb0: thx
<key2>
did you find it by just reading my code or you tried it to find out ?
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<sb0>
reading
<sb0>
doesn't the ODDR have a OBUF as its output?
<sb0>
and the skew on a global clock net is supposed to be small
<larsc>
the difference is less than a 1ns
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<key2>
in endpoints, is it always the source that gives the info from layout to the sink ? or could the sink send something on its Records to the sournce when Acking ?
<sb0>
only source to sink
<key2>
ok
<sb0>
I'm reading Einstein's 1917 paper and he writes that the probability dW of spontaneous emission during the time dt is dW=Adt
<sb0>
there's probably some formalism here I don't understand, because if you integrate this you get W=At, which goes over 1 for large values of t
<cr1901>
isn't dW supposed to represent a *change* in probability anyway?
<sb0>
how do you get the exponential law from this?
<sb0>
yes, and?
<cr1901>
What I'm asking is: Is a differential probability meaningful physical value? They appear in all prob density functions, but I'm not aware that taking the value of a PDF at a single point is a meaningful value.
<cr1901>
I'm getting hung up on how he would've derived this
<sb0>
the equation that gets you exponential law is dW=WAdt, not dW=Adt
<sb0>
maybe W is not a probability.
<cr1901>
Right... any exponential function is of the form f' = kf
<cr1901>
I would have to read the paper. And also brush up on my probability.