<key2>
the reason was really dumb btw :) my programming tool was using the "build" directory, and the project had "wbtest" set as a build directory :) so I was simply writing the wrong file :)
<key2>
that was really dumb
<key2>
worse is that to make sure it works, i made a simple ledblink that eneded up in the blink dir, so when I was writing it down to the fpga, it was blinking as expected :)
<cr1901>
rjo: What is zoll :)?
<larsc>
customs
<key2>
is there a simple example somewhere of how to read/write on wisbhone target bus ?
<whitequark>
yes
<whitequark>
misoc/interconnect/wishbone.py class Interface
<whitequark>
this class has the simulator implementation of a wishbone master
<mithro>
rjo: That looks like a good module for the colors, but it doesn't seem to be the filter/regex matching stuff?
<rjo>
that tool already does pretty much everything you need.
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<sb0>
rjo, what's your idea with the JRC quantum tech report?
<sb0>
or was it just for information?
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<sb0>
is a "spatial light modulator" just an expensive DLP projector without the optics and lamp?
<sb0>
hm, LCD/LCOS, but yes
<sb0>
"It is also possible, using entangled beams, to overcome limits caused by the presence of other types of noise, and by background light, which would make classical imaging impossible, referred to as quantum illumination. "
<sb0>
hm
<sb0>
aren't the single-photon detectors required for entanglement detection saturated by background light?
<sb0>
I can see how such a thing would work theoretically, but not in practice
<rjo>
sb0: that was fyi. but it's related to the flagship project stuff.
<sb0>
this requires the tx logic of a transceiver. with the tx buffer bypassed, it should be possible to recover the cleaned tx clock and use it for other things...
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<sb0>
may be non portable, complex, prone to xilinx bugs and lower jitter performance than the si chip though
<sb0>
lower jitter performance is certain: you have a 7-bit phase tuning word, that you wrap to adjust the transceiver frequency, and which you can only clock at 200MHz
<whitequark>
why do you want to avoid an external clock cleaner?
<sb0>
fewer chips is always good. but it seems to be not worth it here.
<sb0>
it will be a headache and will result in worse performance
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