<whitequark>
ok, I will replicate this on a clean system once I fix the perf issue
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<sb0>
whitequark, are you using the kc705?
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<zoobab>
lekernel is around?
<sb0>
hi zoobab
<sb0>
yes
<zoobab>
Password: 4qk3
<zoobab>
sorry
<whitequark>
sb0: not right now
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<zoobab>
@sb0 see my pm
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<GitHub157>
[migen] jordens pushed 2 new commits to master: https://git.io/vXRey
<GitHub157>
migen/master 2b0d76a Robert Jordens: decorators: inherit docstring and module
<GitHub157>
migen/master 9e76fee Robert Jordens: structure: fixup error message
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<GitHub98>
[artiq] klickverbot opened pull request #608: compiler: Clarify recv_rpc value names and documentation [nfc] (master...recv_rpc) https://git.io/vXRqh
<GitHub79>
[artiq] whitequark closed pull request #608: compiler: Clarify recv_rpc value names and documentation [nfc] (master...recv_rpc) https://git.io/vXRqh
<GitHub127>
[artiq] whitequark pushed 1 new commit to master: https://git.io/vXRmO
<GitHub127>
artiq/master 6e77f65 David Nadlinger: compiler: Clarify recv_rpc value names and documentation [nfc]...
<GitHub139>
[artiq] sbourdeauducq pushed 1 new commit to release-2: https://git.io/vXRY4
<GitHub139>
artiq/release-2 f368e1b David Nadlinger: compiler: Clarify recv_rpc value names and documentation [nfc]...
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<cr1901_modern>
sb0: What is an ElasticBuffer in the Clock Domain Crossings module? And how does it differ from an AsyncFIFO?
<rjo>
cr1901_modern: it resets to half full and doesn't care about tail-head collisions.
<rjo>
and it resets at the right time.
<rjo>
and it is in CDC because it implements a CDC.
<sb0>
cr1901_modern, it's like an AsyncFIFO without flow control. obviously requires that the input rate is equal to the output rate (clocks at the same frequency)
<sb0>
you can use it to transfer data between two clock domains at the same frequency driven by the same oscillator, but with unknown phases
<cr1901_modern>
sb0: Interesting
<cr1901_modern>
"rjo: and it is in CDC because it implements a CDC." So does an Async FIFO
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<cr1901_modern>
why isn't that in CDC :P?
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<cr1901_modern>
while I'm thinking about it, is there any migen module that helps cleanly switch between two clock frequencies, either through a mux or as a result of changing a PLL divider?
<rjo>
cr1901_modern: right. a MultiReg also implements a CDC.
<rjo>
BUFGMUX?
<cr1901_modern>
If I switch too close to when the clock transitions, there could be a duty cycle violation
<rjo>
there is basically no way to write generic clocking logic for xilinx devices. it's all specials.
<rjo>
BUFGMUX fixes that.
<rjo>
or whatever it is in 7 series.
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<cr1901_modern>
Well, if it can't be done generically, I'll do that
<sb0>
cr1901_modern, AsyncFIFO has to be either in the cdc or fifo module, and neither choice is perfect
<cr1901_modern>
sb0: Fair enough. I only mentioned it b/c I'm dense and it took me until this morning to realize that "cdc" stood for "Clock Domain Crossing"
* cr1901_modern
will write docs when he gets the chance
<cr1901_modern>
whereas I've used AsyncFIFO for all my CDC needs up to this point
<cr1901_modern>
MultiReg is just "synchronize one signal unless you've wrapped your input in a GrayCounter" I assume?
<cr1901_modern>
And BusSynchronizer is "synchronize multiple signals when a GrayCounter is inappropriate"?
<cr1901_modern>
Not sure what PulseSynchronizer does yet: Convert's a one-cycle-long pulse in the source to a one-cycle-long pulse in the dest?
<sb0>
cr1901_modern, yes, pulsesynchronizer does that
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<sb0>
gray coding only works when the value of your signal changes at most by 1 at each clock cycle
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<cr1901_modern>
Right. I was commenting on MultiReg potentially accepting > 1 bit signal width
<cr1901_modern>
Which only makes sense if you can GrayEncode
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<cr1901_modern>
sb0: PulseSynchronizer could be used to propogate the reset signal from a CRG in a high-speed clock domain to a lower-speed domain, correct?
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<sb0>
cr1901_modern, you may want to use AsyncResetSynchronizer for this
<sb0>
easier, more robust
<cr1901_modern>
That should map to a device-specific async primitive, correct?
<cr1901_modern>
And Ack.
* cr1901_modern
does some reading
<cr1901_modern>
(All this planning just connect to a single external core that, by design, must operate at a low frequency lmao. Yay...)
<cr1901_modern>
sb0: in a similar vein to AsyncResetSynchronizer, why is MultiReg a Special? It can be dup'ed without device-specific primitives.
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<klickverbot>
whitequark: How much does kernel_invariants do currently (release-2)? I was surprised to find that simple stuff like "def build(self): self.foo = True; @kernel def run(self): if self.foo: … else: …" is not folded away