sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub23> [artiq] whitequark pushed 2 new commits to master: https://git.io/vXaJd
<GitHub23> artiq/master 0e76cbc whitequark: artiq_compile: actually disable attribute writeback....
<GitHub23> artiq/master 67e743d whitequark: conda: use pythonparser 1.0.
<GitHub135> [artiq] whitequark pushed 1 new commit to release-2: https://git.io/vXaJA
<GitHub135> artiq/release-2 b85ab71 whitequark: artiq_compile: actually disable attribute writeback....
<bb-m-labs> build #174 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/174
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<bb-m-labs> build #1075 of artiq is complete: Failure [failed artiq_flash] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1075 blamelist: whitequark <whitequark@whitequark.org>
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<sb0> whitequark, looks good
<sb0> (re. the dashboard)
<sb0> that jtag crash is weird. there's also this message "xhci_hcd 0000:00:14.0: WARN Event TRB for slot 17 ep 2 with no TDs queued?" that floods dmesg
<sb0> well, weird, it's a ftdi-chip after all, it's surprising it hadn't crashed yet
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<sb0> I have added klickverbot as collaborator
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<whitequark> ok
<whitequark> ah right, you reset the hcd
<whitequark> I forgot that you can do that in linux
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<sb0> well the integrated controller may not be the best idea if it cannot be disabled
<sb0> when you really care about DRAM bandwidth, for some applications you want to generate the low-level commands yourself
<larsc> 1k pins, just for the memory!
<sb0> well, microfabricated ones. there are probably a lot more pins between "super logic regions" (let's call them "dies")
<sb0> hm after that USB reset comes another chase for the ttyUSBX nodes of the uart of each board
<sb0> is there a way to reflash CP2103 serial numbers?
<sb0> oh yes
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<sb0> needs the windows utility though as http://cp210x-program.sourceforge.net/ looks broken
<sb0> the FMC transceiver pins are connected to FPGA IOs direct... does that work?
<whitequark> ok, found the LLVM issue that pessimized our code
<GitHub15> [llvm-or1k] whitequark force-pushed artiq-3.9 from 116f21d to 05e3f48: https://github.com/m-labs/llvm-or1k/commits/artiq-3.9
<GitHub15> llvm-or1k/artiq-3.9 5ea766e whitequark: Add new !unconditionally_dereferenceable load instruction metadata....
<GitHub15> llvm-or1k/artiq-3.9 4db1864 whitequark: [SelectionDAG] Fix calling convention in expansion of ?MULO....
<GitHub15> llvm-or1k/artiq-3.9 50cd32d whitequark: [OR1K] Fix merge screwup.
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<whitequark> sb0: which of the ttyUSBs is the console anyway?
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<GitHub175> [migen] jordens pushed 1 new commit to master: https://git.io/vXV6w
<GitHub175> migen/master b716a8b Robert Jordens: SplitMemory: register dat_r selection
<bb-m-labs> build #113 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/113
<bb-m-labs> build #171 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/171
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<bb-m-labs> build #175 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/175
<bb-m-labs> build #1076 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1076
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<whitequark> sb0: uhh
<whitequark> the USB-UART bridge doesn't seem to work properly
<whitequark> it's randoly losing characters and this breaks flterm upload...
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<whitequark> oh, that's your flterm
<GitHub158> [misoc] whitequark pushed 2 new commits to master: https://git.io/vXwen
<GitHub158> misoc/master 967f03a whitequark: flterm: add --output-only option, to avoid requiring a pty.
<GitHub158> misoc/master 50b4dfa whitequark: flterm: add --upload-only option.
<GitHub180> [misoc] whitequark pushed 2 new commits to master: https://git.io/vXwID
<GitHub180> misoc/master 0db54fa whitequark: flterm: nicer progress bar.
<GitHub180> misoc/master b70c484 whitequark: flterm: flush stdout when printing progressbar.
<bb-m-labs> build #172 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/172
<bb-m-labs> build #1077 of artiq is complete: Exception [exception interrupted] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1077
<GitHub170> [artiq] whitequark pushed 1 new commit to master: https://git.io/vXwtU
<GitHub170> artiq/master 3b6cbb1 whitequark: artiq_devtool: implement.
<bb-m-labs> build #1078 of artiq is complete: Exception [exception interrupted] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1078 blamelist: whitequark <whitequark@whitequark.org>
<whitequark> I finally got annoyed enough to replace my SSH hacks with this
<whitequark> rjo: when do you expect the federal funding to dry up, anyway?
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<rjo> whitequark: houh? on what scale? for quantum stuff in general?
<whitequark> rjo: with republican trifecta in office. "small government", all that crap
<rjo> oh. sure. that will be fun. OTOH you could make the point that with trump now likely to increase military spending, this might mean more money for IARPA/DARPA which then goes into quantum stuff.
<larsc> quantum torpedo reasearch?
<rjo> and keep in mind that the EU is dumping probably something like 2 G€ into the quantum flagship project in total.
<whitequark> well. i guess the EU isn't quite as unstable
<rjo> larsc: very much. quantum sensors for INS guidance is a good chunk of their interest
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<rjo> a lot of the instability also comes knee jerk stuff. a few years ago the new boss of IARPA stopped funding of projects with other govt agencies from one day to the next. there was much rejoicing.
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<GitHub175> [migen] jordens pushed 1 new commit to master: https://git.io/vXwG8
<GitHub175> migen/master 6ffffd6 Robert Jordens: sim: Array: handle out of bounds
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<bb-m-labs> build #114 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/114
<bb-m-labs> build #173 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/173
<bb-m-labs> build #1079 of artiq is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1079
<cr1901_modern> rjo: Did you look at the SPI bug? If not, I'll take a look tomorrow. I don't have a board that can run artiq, but I imagine I can dup the bug w/o it.
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<cr1901_modern> rjo: Excuse me, I missed the email where it said you assigned me to it :P (Haven't been on much since... Tuesday night)
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<rjo> cr1901_modern: i assigned it to both of us.
<rjo> cr1901_modern: yes. you can easily reproduce it in simulation.
<rjo> cr1901_modern: thanks!