sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0>
_florent_, did you try running the firmware clocking code? does it work?
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<sb0>
rjo, I'm a bit worried about combinatorial logic used to generate the SPI clock output -- (spi.cg.clk & spi.cs) ^ config.clk_polarity
<sb0>
in theory there is nothing that prevents the synthesizer to generate something that produces glitches. it is better practice to connect the IO to a register output directly.
<sb0>
also, when IOs are connected to register outputs, normally the dedicated registers inside the IOB are used, so the board timing becomes deterministic
<_florent_>
sb0: sorry for the delay, i'm on it. I try to get that working today.
<sb0>
okay, any questions just ask me
<_florent_>
ok will do, thanks
<cr1901_modern>
"the synthesizer to generate something that produces glitches" When would a glitch be generated? Isn't only spi.cg.clk changing during an xfer?
<sb0>
consider a comb circuit with multiple LUTs
<sb0>
and different routing delays
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<cr1901_modern>
I glossed over the "in theory" part. In this case, either the beginning or end of an xfer could have a glitch (IIRC cs/clk_polarity stay stable during the xfer).
<rjo>
sb0: those glitches specifically are fine. they change at different edges. but yes. i guess one could rewrite that.
<sb0>
yes this is unlikely to cause practical problems
<rjo>
sb0: i.e. in this case there won't be glitches.
<sb0>
well you can always make up a circuit that will glitch even if the other inputs aren't changing, but the synthesizer shouldn't do that
<rjo>
sure. it could even do that with a single input. since we are trusting the synthesizer to correctly infer IOBs, it seems reasonable to trust it with not doing that as well.
<bb-m-labs>
build #1722 of artiq is complete: Failure [failed anaconda_upload anaconda_upload_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1722 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<sb0>
bb-m-labs, force build artiq
<bb-m-labs>
build forced [ETA 8h32m20s]
<bb-m-labs>
I'll give a shout when the build finishes
<rjo>
sb0: also, I removed all the 2.0.dev and 3.0.dev artiq and artiq-nist_clock packages from anaconda. and a few old llvm/rustc packages. that freed up 1.5 GB there and sped up "conda install" significantly.
<sb0>
ok
<sb0>
did you write a script for that? or manual removal?
<rjo>
sb0: how do i debug migen's naming algorithm? i have "__main__" appearing due to seemingly random changes. can't seem to find the root cause.
<sb0>
rjo, you can get a SVG of the tree of the name bits that it identified, and which ones it selected. how large is your design that causes the problem?
<sb0>
see _display_tree in fhdl.namer
<sb0>
and _debug
<rjo>
sb0: so is the gist that the namer will not include a object hierarchy level in the names if it is not necessary to disambiguate names?
<GitHub165>
[artiq] dhslichter commented on issue #711: Getting pre-link warnings again today with a fresh install on a new Windows machine. I made sure to update conda, running 4.3.27 py27hcd9d231_0. The only wrinkle I can think of here is that my root environment from which I am creating the new environment to install ARTIQ is a Python 2 environment, but my impression was that conda ought to be able to handle this. Full output is below.... https://g
<GitHub15>
[artiq] dhslichter commented on issue #711: Getting pre-link warnings again today with a fresh install on a Windows 7 machine. I made sure to update conda, running 4.3.27 py27hcd9d231_0. The only wrinkle I can think of here is that my root environment from which I am creating the new environment to install ARTIQ is a Python 2 environment, but my impression was that conda ought to be able to handle this. Full output is below.... https://githu
<GitHub111>
[artiq] dhslichter commented on issue #711: Getting pre-link warnings again today with a fresh install on a Windows 7 machine. I made sure to update conda first, running 4.3.27 py27hcd9d231_0. The only wrinkle I can think of here is that my root environment from which I am creating the new environment to install ARTIQ is a Python 2 environment, but my impression was that conda ought to be able to handle this. Full output is below.... https