<GitHub93>
artiq/rtio-sed 5f083f2 Sebastien Bourdeauducq: rtio/dma: fix signal width
<GitHub93>
artiq/rtio-sed a9c9d57 Sebastien Bourdeauducq: rtio/dma: add full-stack test with connection to RTIO core
<GitHub93>
artiq/rtio-sed 893be82 Sebastien Bourdeauducq: rtio/dma: raise underflow in test
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<sb0>
whitequark, I've been trying to reproduce the DMA/SED issue in gateware simulation but could not. it would seem that the gateware is behaving itself.
<sb0>
on the other hand I don't see any firmware change that could have caused this
<sb0>
it's really annoying
<whitequark>
sb0: I'll get back to poking firmware in a bit, let's see if I can verify some of my guesses
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<GitHub63>
[artiq] jordens commented on issue #793: With `f_data = 600 MHz` and 4x DAC interpolation to 2.4 GHz, from the `0.2 f_data` transition skirt width of the AD9154 interpolation we have:... https://github.com/m-labs/artiq/issues/793#issuecomment-335080384
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<GitHub177>
[artiq] jordens commented on issue #793: They were worried about spur free dynamic range within 150-260 MHz. Since the AA filter only suppresses to 58 dB, that will be limiting for f_RTIO=125 MHz.... https://github.com/m-labs/artiq/issues/793#issuecomment-335146871
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<shuffle2>
i'd like to use migen+zedboard to make a design that exposes bram to the arm core. is that (bram, various axi, ...) already usable from migen somehow? or would i need to lift the verilog/vhdl out of vivado somehow and wrap it?
<shuffle2>
also migen defaults to using ISE with zedboard atm. i changed it to vivado and it works fine for some simple thing...(really, maybe migen should just try both for xilinx targets?)
<GitHub45>
[artiq] jordens commented on issue #793: With `f_data = 600 MHz` and 4x DAC interpolation to 2.4 GHz, from the `0.2 f_data` transition skirt width of the AD9154 interpolation we have:... https://github.com/m-labs/artiq/issues/793#issuecomment-335080384
<GitHub115>
[artiq] hartytp commented on issue #793: > They were worried about spur free dynamic range within 150-260 MHz. Since the AA filter only suppresses to 58 dB, that will be limiting for f_RTIO=125 MHz.... https://github.com/m-labs/artiq/issues/793#issuecomment-335149546
<GitHub116>
[artiq] jordens commented on issue #793: I don't see a roadblock. It will just take longer and more fiddling/trial and error to deliver a 1 GHz f_data bitstream than 600 MHz. And once there are problems with e.g. DRTIO there will be a need to exclude electrical issues and hence the need for a slower design anyway. https://github.com/m-labs/artiq/issues/793#issuecomment-335153967
<rjo>
shuffle2: bram is inferred (i.e. integrated). redpid has some code you can reuse for that.
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