<GitHub149>
[smoltcp] whitequark commented on pull request #72 5682ccf: I think IPv6 addresses are typically constructed from 16-bit parts, not 8-bit parts. https://git.io/vFugu
<GitHub86>
[smoltcp] whitequark commented on pull request #72 5682ccf: This PR would also be well served if you added an IPv6 parser to it. https://git.io/vFugw
<GitHub28>
[smoltcp] whitequark commented on pull request #72 5682ccf: ... and a missing newline https://git.io/vFugg
<GitHub143>
[smoltcp] whitequark commented on pull request #72 5682ccf: Extra newline https://git.io/vFugz
<GitHub64>
[smoltcp] whitequark commented on pull request #72 5682ccf: There's already a (commented) case below that catches this. https://git.io/vFuga
<GitHub100>
[smoltcp] whitequark commented on pull request #72 5682ccf: I wonder what should we do with IPv6-mapped IPv4 addresses. I *think* the conversion should happen on a layer above this, though, since IPv6-mapped IPv4 addresses shouldn't really ever appear *on wire*. https://git.io/vFug6
<GitHub24>
[smoltcp] whitequark commented on pull request #72 5682ccf: Let's not split it into modules yet, I like the regularity of the current module tree a lot. https://git.io/vFugK
<GitHub106>
[smoltcp] whitequark commented on pull request #72 5682ccf: Should also have `from_parts(&[u16])` and (bikeshed the name) `write_parts(&mut [u16])` https://git.io/vFug2
<GitHub82>
[smoltcp] whitequark commented on pull request #72 5682ccf: Split this line in two please https://git.io/vFugV
<GitHub43>
[smoltcp] whitequark commented on pull request #72 5682ccf: Smoltcp doc comments all have a dot at the end of the first sentence. https://git.io/vFugr
<mithro>
That is my random links regarding PCB stuff
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<mithro>
I'm very interested in trying to make it easy to snap together FPGA based designs
<cr1901_modern>
Is this about pcbhdl?
<cr1901_modern>
mithro: ^
<mithro>
Yes
<mithro>
Just meet whitequark in person :-)
<cr1901_modern>
oh cool, lucky you
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<whitequark>
mithro: oh very cool, your unit tests is exactly what azonenberg wanted from pcbhdl
<whitequark>
we should join forces!
<mithro>
whitequark: Mine do not really work yet - I only got as far as describing what I wanted and parsing the info
<whitequark>
sure, but that is already valuable, because it constrains the space of requirements
<GitHub139>
[smoltcp] whitequark commented on issue #77: The frame check sequence, just like the preamble and start delimiter, are handled by hardware. https://git.io/vFu1y
<GitHub37>
[smoltcp] whitequark commented on issue #77: Note the difference between ethernet _packet_ and ethernet _frame_; the packet includes preamble and FCS, whereas the frame does not. https://git.io/vFu19
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<GitHub127>
[smoltcp] LuoZijun commented on issue #77: @whitequark ... https://git.io/vFuMg
<GitHub0>
[smoltcp] LuoZijun commented on issue #77: @whitequark ... https://git.io/vFuM5
<GitHub171>
[smoltcp] LuoZijun commented on issue #77: @whitequark ... https://git.io/vFuM5
<GitHub136>
[smoltcp] LuoZijun commented on issue #77: @whitequark ... https://git.io/vFuM5
<rjo>
whitequark: how are the smoltcp issues coming along?
<rjo>
mithro: any chance those features will find their way back into kicad?
<cr1901_modern>
rjo: Would you have time this morning to re-look over my PR?
<rjo>
cr1901_modern: will do.
<cr1901_modern>
Tyvm. Take your time of course, just wanted to touch base. I wish to add a new platform (tinyfpga-b), but the current changes are a prerequisite.
<rjo>
sure. but then you want to make it so that yosys can be used in all those situations. then there doesn't seem to be much room for abstracting over it. the special_overrides are platform and toolchain specific, the yosys commands and options are as well. the only thing that might be common is the attr_translate stuff.
<cr1901_modern>
AIUI you would prefer that I provide a "syntheis_commands" template that gets concatenated to the required yosys commands in the output .ys file?
<cr1901_modern>
And just rely on the user to ensure at least one of the commands generates an output BLIF (for the pnr)
<cr1901_modern>
Additionally, you want the *_opt fields removed and replaced with a command file template?
<cr1901_modern>
I agree the current logic to generate the command file isn't great, but it's done like that so the build correctly fails if any command fails on Windows
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<rjo>
with a list of yosys command templates (see the additional comment) and a list of batch command templates. platforms can then just copy and alter or append()/insert() those lists. trying to parametrize the batch file into x/y/z_opt and the yosys script with post/pre/x/_synth_commands will not work in the long run.
<rjo>
i.e. just merge those parametriziations.
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<rjo>
cr1901_modern: almost. cut out that intermediate layer.
<cr1901_modern>
intermediate layer?
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<cr1901_modern>
I'm not sure I follow. Though one weakness as-is is that the user needs to figure out which index is "pre_synth" and the other "post_synth"
<rjo>
cr1901_modern: ys_contents = "\n".join(_.format(build_name=build_name, ...) for _ in self.synthesis_template)
<rjo>
and have the user mess with self.synthesis_template
<rjo>
plus a helper for read_files
<cr1901_modern>
is it okay that pre_synth/post_synth become no-ops by default?
<rjo>
remove them. the user can inject that stuff into synthesis_template (maybe find a better name for that)
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<cr1901_modern>
Alright let me update the file
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<cr1901_modern>
rjo: I should prob remove "{migen_attrmap}" and "{read_files}", and "{synth_override}" too. The user can override them directly as needed.
<cr1901_modern>
err, maybe not read_files
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<cr1901_modern>
rjo: plus a helper for read_files <-- a helper function? We won't know the all the files to read until build() runs.
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<rjo>
cr1901_modern: yeah. you'll still need code for the read_files stuff. but that's fine.
<rjo>
cr1901_modern: yes. that looks good.
<cr1901_modern>
rjo: Okay, so I have an idea... "{read_files}" is replaced by the return value of a helper method like you said. By default, it just does what lines 120-125 does.
<cr1901_modern>
But you can override that function to do special processing if needed?
<cr1901_modern>
Was that your intent? If so, is it better to specify an override as an input argument to build(), just like how build_name is?
<cr1901_modern>
a read_files override*
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<rjo>
no. let that code be a method and people can override the method.
<cr1901_modern>
Okay. All changes you requested incoming in 5 mins
<GitHub34>
[smoltcp] dlrobertson commented on issue #69: Thanks for the reviews. The final product was much much better than the first few revisions https://git.io/vFzfc
<cr1901_modern>
rjo: All changes you requested implemented. I'm taking a break right now. Please take a look when you have the chance >>
<cr1901_modern>
and then we can perhaps figure out what color to paint the shed? :)
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<rjo>
cr1901_modern: all good.
<cr1901_modern>
rjo: Excellent. Only concern left is: what should I call synthesis_template and build_template?
<cr1901_modern>
(We can worry about this later if you wish, or you can change it to whatever you want and I'll update accordingly)
<rjo>
yosys_template and build_template?
<cr1901_modern>
works for me
<cr1901_modern>
rjo: Done. Tyvm :D
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<_florent_>
sb0: ok for the dram, i'm looking at the bridge... (it seems to be related to the rx path on ultrascale, tx on ultrascale and rx/tx on artix seem fine)