sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<FelixVi> It's broken and doesn't add the top file
<FelixVi> verilog include paths aren't set for the top file
<FelixVi> I don't see where they get added anywhere in migen
<FelixVi> when running misoc, they do get set
<FelixVi> gotta run for now
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<cr1901_modern> Why is he running into so many problems ._.?
<cr1901_modern> I have absolutely no clue reading it...
<sb0> _florent_, good, I'll have a look, thanks.
<sb0> _florent_, ethernet still needs fixing
<cr1901_modern> "It's broken and doesn't add the top file" Gah, this not tell me anything!
<sb0> _florent_, nope. bridge still doesn't work. please try on our boards via ssh
<sb0> "waiting for AMC/RTM serwb bridge to be ready..." and stops there
<sb0> ah it worked on one of the boards
<sb0> okay, seems to work most of the time...
<sb0> on both boards
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<sb0> for testing the hmc830, do I have to feed a 100MHz clock to the SMA plug on the front panel?
<sb0> _florent_, what is the problem with the hmc830?
<sb0> _florent_, what did you change to ad9154.rs? latest commits are ~11 days old...
<GitHub133> [artiq] sbourdeauducq commented on commit cd83b71: It's not a memory... https://github.com/m-labs/artiq/commit/cd83b71d92fd01dd1599279028ac214c2ab1f90d#commitcomment-25705769
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<FelixVi> Does the papilio pro target get tested for xst file generation in some test?
<FelixVi> I'm still having issues with that as no xst file is generated at all
<FelixVi> The weird thing is that misoc works fine on that target
<FelixVi> Here's the test file I'm using: https://pastebin.com/eYmnTddC
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<GitHub54> [smoltcp] sbourdeauducq commented on issue #68: @whitequark ping https://github.com/m-labs/smoltcp/issues/68#issuecomment-345490298
<FelixVi> OK, adding a dummy directory as verilog include path makes things work. There's probably a better solution, but I couldn't figure out what is adding include paths if all you do is blink a LED
<sb0> what is the problem?
<sb0> there shouldn't be any include path in your example
<FelixVi> migen doesn't generate xst files if vincpaths is not set
<sb0> ?
<FelixVi> if there isn't any, no xst file gets written
<sb0> ah
<sb0> I suppose tools.write_to_file got the wrong indent ...
<sb0> here
<FelixVi> alright, that makes sense :)
<FelixVi> let me try
<sb0> let me check the git log
<sb0> well the original migen doesn't have the problem.
<FelixVi> yeah, alright that was it
<FelixVi> ah, that's dumb - sorry about the confusion
<FelixVi> that must have gotten messed up when we added sanitize()
<FelixVi> the good news is with that patch, both ISE toolchain and programmers work :)
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<FelixVi> sb0: Are you guys using FTDI ICs like FT232H and FT2232H in async FIFO or sync FIFO mode?
<FelixVi> ah, found it - for those interfaces "usb_fifo" is used, right?
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<sb0> I think _florent_ uses those
<FelixVi> as far as I can see, it's for async FIFO
<FelixVi> I'm adding a platform for Numato Saturn
<GitHub156> [misoc] sbourdeauducq pushed 1 new commit to master: https://git.io/vFHu4
<GitHub156> misoc/master a427a83 Sebastien Bourdeauducq: liteeth/1000basex: PCS fixes
<bb-m-labs> build #281 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/281
<FelixVi> sb0: where do I find the variants of xc6slx9-csg324?
<sb0> variants?
<FelixVi> It looks like there's different versions for the same package and size
<sb0> speed grade?
<FelixVi> like xc6slx9-2csg324 in lx9_microboard and xc6slx9-csg324-2 in mimasv2
<FelixVi> both lx9 csg324 sg -2
<FelixVi> what I need is lx45-csg324 in sg -2
<FelixVi> is that just xc6slx45-csg324-3 then?
<FelixVi> but xc6slx45-csg324-2 bc it's sg 2
<FelixVi> the lx9 variants confused me
<sb0> I think both those "variants" mean speed grade 2
<FelixVi> is there a listing of them somewhere or is the naming following bscan files?
<sb0> just written differently
<sb0> I don't think bscan files contain speed grades, though I may be wrong
<sb0> should be in xst docs
<sb0> or somewhere else xst-related
<FelixVi> I couldn't track down what XilinxPlatform does with that info other then passing it along
<sb0> nothing
<sb0> it just passes to xst
<FelixVi> ah, I'll check there
<GitHub160> [misoc] sbourdeauducq pushed 1 new commit to master: https://git.io/vFHu7
<GitHub160> misoc/master be3c1a9 Sebastien Bourdeauducq: liteeth/1000basex: register config reg in PCS when ack is asserted
<bb-m-labs> build #282 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/282
<FelixVi> sb0: Thanks, got it. Could not find a list from Xilinx, so needed to create an ISE project with the GUI to find out...
<GitHub26> [misoc] sbourdeauducq pushed 1 new commit to master: https://git.io/vFHux
<GitHub26> misoc/master 30ea1a4 Sebastien Bourdeauducq: liteeth/1000basex: add basic PCS loopback test
<bb-m-labs> build #283 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/283
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<sb0> how do I get 125MHz GbE clocks out of the xilinx trash? is there a better way than additional PLLs and manual gearbox?
<FelixVi> i usually use pll_adv
<FelixVi> there's pll_adv and dcm, depending on what you need
<FelixVi> 0 and 180 degrees at 125 MHz?
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<sb0> that's the manual technique
<sb0> but there is already a 125MHz clock coming in
<sb0> but the xilinx trash insists on dividing it by 2
<FelixVi> you should be able to go to a bufg directly
<sb0> not with transceivers
<FelixVi> oh, is this serdes out?
<sb0> the multi-Gb stuff
<FelixVi> is this GbE or XAUI?
<sb0> with dedicated pins and probably an entry for some "most imbecilically designed FPGA hard block" competition
<sb0> 1000BASE-X
<sb0> at least that's a relatively sane protocol, unlike things like SATA ...
<FelixVi> true, but I'm confused why it's serial
<sb0> this is what drives SFPs, which then convert it directly to light pulses on fibers
<FelixVi> oh, so no gmii intf
<sb0> no
<FelixVi> sry, that I haven't done anything with
<sb0> a gmii chip would then have those 1000BASE-X signals on the other end.
<FelixVi> for serdes one can use bufpll, but not sure if transceivers accept that, too
<sb0> no. the transceivers are a world of their own.
<FelixVi> k, sorry i can't help -.- but sounds like I should get a board with transceivers to play with at some point :)
<sb0> I recommend you try something else than Altera and Xilinx
<sb0> I already know that those are trash, so I'm happy to learn more about alternatives
<FelixVi> lattice or actel might be options
<FelixVi> but I don't know much about either one
<sb0> there were those "polarfire" fpgas with transceivers that looked interesting
<sb0> but non-volatile and with a rather limited programming cycle rating
<FelixVi> lattice seems lower end and actel is good for space applications because they got a lot of rad hardened stuff, isn't it?
<sb0> yes. maybe their cycle rating is overly pessimistic.
<FelixVi> yeah, those look interesting - I wonder if the JESD204B core is free :)
<FelixVi> but their maccs are just as wide as spartan6 ones
<sb0> with a transceiver that doesn't suck, JESD204 isn't very complicated
<FelixVi> I'd love to play with some fast data converters
<FelixVi> didn't ARTIQ just get 2 Gbps DAC support?
<sb0> we have this
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<FelixVi> can you guys get boards stuffed cheaply in hk? :)
<FelixVi> it tends to be a bit on the expensive side here in the us
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<sb0> not in hk but in shenzhen yes
<FelixVi> sb0: according to the datasheet the ad9154 has a data rate of 1.096 GSPS
<sb0> those boards aren't made in shenzhen though
<FelixVi> not sure if I missed something, but is it really 1.2 GS/s?
<sb0> yes
<FelixVi> 2x int?
<sb0> wow the new vivado gui looks like windows 10
<FelixVi> I looked at the ad9154, but then went with a 500 MSPS parallel DAC because it was easier
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<_florent_> sb0: for the hmc830, yes you have to feed a 100Mhz clock to the SMA
<_florent_> sb0: it's not generating any frequency on the output on my board while in my initial test IIRC i was able to output something
<GitHub146> [artiq] enjoy-digital pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/dfdd2dd9e65b4126f40307bb9bd05542455e17f0
<GitHub146> artiq/master dfdd2dd Florent Kermarrec: gateware/targets/sayma_amc_standalone: revert self.add_wb_slave on serwb
<_florent_> FelixVi: https://github.com/enjoy-digital/liteusb/blob/master/liteusb/phy/ft245.py supports sync/async fifo modes
<_florent_> FelixVi: just renaming litex.gen to migen, litex.soc to misoc, should work
<_florent_> sb0: for your 125Mhz clock, you should be able to use ODIV2 of IBUFDS_GTE3
<_florent_> sb0: with REFCLK_HROW_CK_SEL=0b00, ODIV2=i_I, no divisision
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<GitHub64> [artiq] jordens commented on commit cd83b71: Please undo that https://github.com/m-labs/artiq/commit/cd83b71d92fd01dd1599279028ac214c2ab1f90d#commitcomment-25708639
<GitHub158> [artiq] enjoy-digital commented on commit cd83b71: sorry, i was using it as a memory on my test target, reverted. https://github.com/m-labs/artiq/commit/cd83b71d92fd01dd1599279028ac214c2ab1f90d#commitcomment-25708652
<_florent_> sb0: ad9154.rs patch https://hastebin.com/okujakoyiy
<bb-m-labs> build #891 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/891
<bb-m-labs> build #1777 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1777 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
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<GitHub198> [artiq] enjoy-digital commented on commit cd83b71: Can you connect sawg to jesd? thanks. (this and bellow) https://github.com/m-labs/artiq/commit/cd83b71d92fd01dd1599279028ac214c2ab1f90d#commitcomment-25708997
<travis-ci> [rust-managed] whitequark pushed 2 new commits to master: https://github.com/m-labs/rust-managed/compare/a4f43056c1a2...629a6786a1cf
<travis-ci> rust-managed/master ef99a8b whitequark: Collect code coverage.
<travis-ci> rust-managed/master 629a678 whitequark: Add tests for ManagedMap::Borrowed and fix some bugs.
<travis-ci> m-labs/rust-managed#26 (master - 629a678 : whitequark): The build passed.
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<GitHub143> [artiq] jordens pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/d1a7c1c3a10949420892e47f39326fccbd15f2b9
<GitHub143> artiq/master d1a7c1c Robert Jordens: sayma_amc_standalone: connect sawg to jesd again
<GitHub172> [artiq] jordens commented on commit cd83b71: done. but the above had nothing to do with that. https://github.com/m-labs/artiq/commit/cd83b71d92fd01dd1599279028ac214c2ab1f90d#commitcomment-25711399
<bb-m-labs> build #892 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/892
<bb-m-labs> build #1778 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1778 blamelist: Robert Jordens <rj@m-labs.hk>
<GitHub191> [smoltcp] LuoZijun commented on issue #82: @whitequark i think his mean is platform api ( `phy` ) .... https://github.com/m-labs/smoltcp/issues/82#issuecomment-345519504
<GitHub88> [smoltcp] LuoZijun commented on issue #82: @whitequark i think his mean is platform api ( `phy` ) .... https://github.com/m-labs/smoltcp/issues/82#issuecomment-345519504
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<GitHub61> [migen] jordens pushed 1 new commit to master: https://git.io/vFHFp
<GitHub61> migen/master a4fde6d Robert Jordens: kasli: review v1.0 (=v1.0rc3) and add eem1
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<FelixVi> rjo: could you look over a platform I am trying to add? For some reason code gets optimized away, so there must be a bug in there
<bb-m-labs> build #203 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/203
<FelixVi> this is the platform
<FelixVi> and this is the test code I am trying to run
<cr1901_modern> plat.request("led_pins").leda.eq(m.d1)
<FelixVi> ah, thanks! :)
<cr1901_modern> If you use Subsignals, you have opted into the returned type having fields which have the actual signals
<cr1901_modern> (This isn't how I'd do it personally for LEDs, but it's _your_ design :)...)
<FelixVi> I wasn't trying to, but couldn't figure out how to not use them
<cr1901_modern> my_led_pins = [("led_pins", 0,  Pins("P2:0")),   ("led_pins", 1, Pins("P2:1")), ]
<FelixVi> yeah, that's what I wanted to do
<FelixVi> so that they can be assigned in a loop
<cr1901_modern> What's wrong with that then?
<FelixVi> nothing, just couldn't figure out how to do it
<FelixVi> haven't spend much time to work with migen syntax
<cr1901_modern> Oh... guess I could do a better job explaining it in my post then
<FelixVi> until now, I was fighting OS related issues
<FelixVi> well, that's the one line that is missing ;)
<FelixVi> but it helped me a lot to put the rest of the platform together
<FelixVi> are you aware of any misoc tutorial or write ups? once I get this working I'd love to try running some code on the new platform
<cr1901_modern> None that aren't out of date. I mostly suggest the examples or looking at misoc cores
<FelixVi> ah, I was told to use flterm
<FelixVi> but do I compile code with lm32-elf-gcc and feed that to flterm once the bios is up?
<cr1901_modern> Yea, once flterm is running it'll look for a magic string that the MiSoC BIOS provides. If it sees that string, flterm will respond with its own magic string
<cr1901_modern> and a xfer will begin automatically without user intervention
<FelixVi> ah cool, so I should be pretty close then actually
<FelixVi> I didn't seem like that for a while now...
<FelixVi> cr1901_modern: bitfile generation and upload from the test file for the new platform works
<FelixVi> thanks for all the help getting started
<cr1901_modern> Yw. And that's good. Now it's time to make a PR!
<FelixVi> cr1901_modern: I'll test drive it a little more first - wanna check on SDRAM, serial etc
<FelixVi> but should see that as I play with misoc
<FelixVi> gotta run for a while, but I'll make a misoc platform next to make sure peripherals work
<GitHub73> [artiq] enjoy-digital commented on commit cd83b71: thanks https://github.com/m-labs/artiq/commit/cd83b71d92fd01dd1599279028ac214c2ab1f90d#commitcomment-25713750
<GitHub91> [artiq] jordens pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/ecfe2e40eefc2dbc0f2d4a3a23a69728eff4b6f6
<GitHub91> artiq/master ecfe2e4 Robert Jordens: sayma_amc_standalone: rtio channels for both sawg groups
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<GitHub90> [migen] jordens pushed 2 new commits to master: https://git.io/vFHAd
<GitHub90> migen/master d1700ee Adam Greig: build/platforms/de0nano: Fix incorrect sw1 pin assignment: T9->T8
<GitHub90> migen/master 821fbdc Robert Jördens: Merge pull request #89 from adamgreig/de0nano...
<bb-m-labs> build #893 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/893
<bb-m-labs> build #204 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/204
<bb-m-labs> build #1779 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1779 blamelist: Robert Jordens <rj@m-labs.hk>
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<FelixVi> for ddr2 (as used for pipistrello), we're using 4xserdes as seen here - self.specials += Instance("BUFPLL", p_DIVIDE=4, - , right?
<FelixVi> so self.cd_sys.clk needs to be a quarter of the sdram wr rd clock from the main PLL
<FelixVi> is that ratio fixed or do you think using 8xserdes will work as well? I'm struggling a bit to tweak up my new platform (lx45 but speed grade 2, not sg3 as the pipistrello)
<FelixVi> I don't get why people use sg2 and don't just spend the extra $5
<FelixVi> does misoc check for sdram setup times based on the pll phase settings? I seem to have some setup time issues which aren't reported, yet memtest fails
<cr1901_modern> That should be Xilinx's job
<cr1901_modern> And timing analysis should be able to relate the phase of the sdram clk to the input clk
<FelixVi> crg_pll_3 (ddr clock) only has a minperiod constraint as far as i can see
<cr1901_modern> Oh I think you're doing something different from me then
<FelixVi> but crg_pll_2 (fpga data and addr timing) has both setup and hold
<FelixVi> it's for ddr2 memory using serdes
<FelixVi> but as I fail memtest, something about my pll setup must be screwy
<FelixVi> oh and this is at 40 MHz, so timing should be pretty easy to meet
<FelixVi> so I messed something up big time, but I don't see where I went wrong
<cr1901_modern> I've little experience w/ ddr2, so I'm not sure I can help :/
<FelixVi> 20 MHz core, 40 Mhz DDR, 80 MHz wr/rd strb
<cr1901_modern> Perhaps it is too slow for the memory and contents are being lost before refresh?
<FelixVi> same memory as pipistrello (let me check on speed grade) - but at 40 MHz that probably doesn't matter
<FelixVi> that could be... let me run at twice the speed - I was getting timing violations north of 80 MHz, but 40 MHz core should run
<cr1901_modern> rjo: https://github.com/m-labs/migen/pull/88#pullrequestreview-77649963 You approved the changes as-is (i.e. without me needing to modify anything)?
<FelixVi> so, pipistrello has sg -5
<FelixVi> saturn should have -5 as well
<FelixVi> hmm, I find that confusing
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<cr1901_modern> Which DDR controller are you using? MiSoC's?
<FelixVi> yeah, currently s6halfrate
<FelixVi> i'm thinking about trying out quarter rate, but then I have to make sure I edit the clock tree accordingly
<FelixVi> fixing this would probably be better
<FelixVi> S6HalfRateDDRPHY to be exact
<FelixVi> timing passes, bios crc is good but memtest fails
<cr1901_modern> Perhaps you should ask _florent_ for help when he's aroundf
<FelixVi> does one need to modify bitslip setting when the clock rate changes?
<FelixVi> I adjusted the phases so that the clock leads by the same amount of time, also without success
<FelixVi> let's see if it runs at 30 MHz core...
<FelixVi> 40 gave me timing errors
<FelixVi> still no love from the sdram...
<FelixVi> I'll wait for rjo or _florent_ then
<FelixVi> 20 MHz version with adjusted phase is pushed on github
<FelixVi> this is the latest version where the vco also runs at fmax (doesn't fix the issue, though)
<FelixVi> pin assignment is identical to pipistrello (same MCB), but speed grade is different as mentioned above
<FelixVi> the rest should pretty much be identical, so I think it has to do with frequency scaling the DDRPHY
<FelixVi> this is the timing report:
<FelixVi> what I find a bit weird is that actual period on pll[5] aka sys_clk is 11.286ns on pipi while mine is 29.568ns
<FelixVi> only difference should be speed grade, number of routed signals between the two designs is the same
<FelixVi> this is the pipistrello timing report: https://pastebin.com/QABNeyx6
<FelixVi> any help is appreciated! I'm starting to wonder if too much slack is a problem...
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