sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0>
cr1901_modern, it should not be legal. it's a bug.
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<cr1901_modern>
sb0 (clearly I need to sleep): I created that contrived example after noticing that you allow BUILD_LIST opcodes in tracer,get_var_name.
<cr1901_modern>
Idk why you allow BUILD_LIST at all, but I'm sure if you look at the disassembly of that stupid contrived edge case I made you'll immediately see why it succeeds.
<GitHub186>
[artiq] sbourdeauducq commented on issue #854: @gkasprow Just looking at a different way of fixing things, in case the routing to non-clock-capable pins is causing excessive problems. Can the PHY be set up in a non-standard way to **receive** both the TX and the RX clock that would be generated by the FPGA, in either "RGMII" (1Gbps 125MHz DDR) or "MII" (100Mbps 25MHz SDR) modes? https://github.com/m-labs/artiq/i
<GitHub183>
[artiq] sbourdeauducq commented on issue #854: @gkasprow Just looking at a different way of fixing things, in case the routing to non-clock-capable pins is causing excessive problems. Can the PHY be set up in a non-standard way to **receive** both the TX and the RX clocks that would be generated by the FPGA, in either "RGMII" (1Gbps 125MHz DDR) or "MII" (100Mbps 25MHz SDR) modes? https://github.com/m-labs/artiq/
<sb0>
cr1901_modern, iirc BUILD_LIST is allowed somewhere else, not in that function that is used for CSRs, and that's for things like self.x = [Signal() for _ in range(y)]
<rohitksingh_work>
sb0: wishbone slave interface is most likely broken, which I'll fix. Block RAM to CPU interface should be fine.
<rohitksingh_work>
sb0: If the structure of the modifications is fine, I'll go ahead and fix the wishbone interface (which currently is broken most likely) and add tests for testing the modifications
<rohitksingh_work>
sb0: Apologies in advance if you find anything horrible (beginner). I would very much like to receive as many constructive criticisms, reviews and suggestions as possible.
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<cr1901_modern>
sb0: I have an idea to refactor the code that's semantically equivalent to the current get_var_name code and will fix the bug. I'll code it this morning and you can critique it when you have the chance.
<cr1901_modern>
This refactor will also make Python 3.6 support trivial
<rohitksingh>
sb0: saw your comments from initial review! thanks! I'll fix those as well as other issues (like true dual port ram etc). And we are going to use same clock for Wishbone slave interface as for mor1kx core or different asynchronous clocks?
<rohitksingh>
I'm just hoping the structure of the modifications is as envisaged by you
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<sb0>
_florent_, any update? if you're stuck on the serwb bug please make some progress on drtio
<sb0>
rohitksingh, same clock
<sb0>
rjo, which is the most mature dds? 9910 or 9912? I'd like to ship that one to SYSU to avoid cumulating delays
<sb0>
(if possible)
<cr1901_modern>
sb0: Bug is more complicated than I thought... you'd expect the following code to work (i.e. name from MySpecialCSRStatus to be inferred), correct? https://hastebin.com/uporeripam.py
<cr1901_modern>
B/c this also doesn't work, and from the limited print() debugging I can do (I _hope_ pdb lets me run arbitrary python), get_obj_var_name isn't finding the correct frame
<cr1901_modern>
to inspect when given code like this
<sb0>
cr1901_modern, uh, no that code is quite broken
<cr1901_modern>
how so?
<sb0>
you're calling the constructor of MySpecialCSRStatus on MySpecialModule, which is not a derived class
<sb0>
also expect __init__ to return a value, which it doesn't
<sb0>
self.dummy is None.
<whitequark>
sb0: we need to increase the amount of ethernet rx buffers
<sb0>
whitequark, yeah go ahead
<cr1901_modern>
sb0: You might not want to re-look at my previous example then
<sb0>
though I'm surprised lwip seemed to work quite well
<whitequark>
sb0: oh everything works fine
<whitequark>
the reassembler does the job perfectly
<whitequark>
it's just that I don't think we should have packets dropped at all
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<cr1901_modern>
(Example in the issue I opened has been modified. I can still produce the issue.)