19:07 <GitHub170> [artiq] gkasprow commented on issue #854: I think I know where the problem is. I implemented simple condition in MMC firmware that resets the PHY chip after FPGA gets configured and DONE goes low.... https://github.com/m-labs/artiq/issues/854#issuecomment-348584527

19:11 <GitHub195> [artiq] gkasprow commented on issue #854: I will test it on Monday. https://github.com/m-labs/artiq/issues/854#issuecomment-348587253

19:49 <G33KatWork> hi, I have a question about litedram. Suppose I have a board with 2 16 bit DDR3 chips on it where the manufacturer tried to save pins and didn't wire up the 4 data mask pins. Now Xilinx' MIG only supports an AXI interface if these pins are actually connected to the chips. Does litedram need them, too for a memory mapped interface? All I want for easy testing right now if everything works is an easy way

19:49 <G33KatWork> to read and write to/from the memory

19:52 <G33KatWork> is that even the right channel to ask such a question?

19:55 <X-Scale> G33KatWork: there's also ##fpga

20:23 <G33KatWork> okay, litedram uses the data mask pins. just found it in the code

21:48 <GitHub155> [artiq] enjoy-digital commented on issue #860: It would be interesting to look at the output of the HMC7043 to be sure the clocks are clean. (from the first tests i remember it was not the case, so this could maybe explain the intermittents JESD failures). https://github.com/m-labs/artiq/issues/860#issuecomment-348623163

22:07 <bb-m-labs> build #927 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/927

22:10 <bb-m-labs> build #1811 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1811 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>

22:37 <_florent_> sb0/rjo: drtio is working fine with 150Mhz refclk / 3Gbps linerate :)