01:12 <sb0> whitequark, this is sayma, so ethernet is broken, and what the firmware typically does at startup is freeze on a broken serwb

01:22 <GitHub54> [artiq] sbourdeauducq commented on issue #854: @gkasprow In standard MII mode, with no link present, is the PHY toggling the TX and RX clocks? They are not toggling here, which might point to a problem other than media converter incompatibility. https://github.com/m-labs/artiq/issues/854#issuecomment-354519805

01:22 <luozijun> @whitequark hi

03:41 <sb0> what is this crap on IBUFDS_GTE3: "REFCLK_ICNTL_RX, 2-bit Binary, Reserved. Use the recommended value from the Wizard."

04:06 <sb0> anyway the IBUFDS_GTE3 output is toggling at the correct frequency. so I don't know why the CPLL junk is not working.

04:12 <sb0> ah I don't have the correct reset sequence...

04:14 <GitHub84> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/6e0288e56807a494f1119de0132201f2cc3ea2ee

04:14 <GitHub84> artiq/master 6e0288e Sebastien Bourdeauducq: drtio: fix GTH CPLL reset

04:43 <bb-m-labs> build #1014 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1014

04:50 <bb-m-labs> build #663 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/663

04:53 <bb-m-labs> build #1894 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1894

08:38 <whitequark> luozijun: hi

11:04 <GitHub66> [artiq] gkasprow commented on issue #854: @sbourdeauducq I don't know. I observed both clock with link up.... https://github.com/m-labs/artiq/issues/854#issuecomment-354540258

14:08 <sb0> debugging drtio with the 1v8 bug is fucking annoying

14:10 <sb0> I have to power cycle boards 2-3 times every time I'm loading a bitstream, because at least one of them failed

14:11 <sb0> they also fail in the middle of something else, and then I have to guess whether my code crashed or the 1v8 supply broke

14:14 <sb0> sayma3 is also still unusable due to the scansta rtm bug...

14:14 <sb0> sigh

14:15 <sb0> I'm getting one 3Gbps link unidirectional link to work, the other direction repeatedly fails even when swapping bitstreams

14:16 <sb0> (works = when the pile of jtag, power supply, etc. bugs decide not to manifest themselves)

16:49 <GitHub113> [artiq] hartytp commented on issue #860: Did this fix the HMC830 problem?... https://github.com/m-labs/artiq/issues/860#issuecomment-354555840

16:59 <GitHub157> [artiq] hartytp commented on issue #860: Note to self, cf https://github.com/m-labs/sinara/issues/216#issuecomment-314706532 https://github.com/m-labs/artiq/issues/860#issuecomment-354556347

17:12 <GitHub176> [artiq] enjoy-digital commented on issue #860: Not sure it could be related, but the say i was testing hmc803/hmc7043 i also did this:... https://github.com/m-labs/artiq/issues/860#issuecomment-354556998

17:12 <GitHub63> [artiq] enjoy-digital commented on issue #860: Not sure it could be related, but the day i was testing hmc803/hmc7043 i also did this:... https://github.com/m-labs/artiq/issues/860#issuecomment-354556998

17:15 <GitHub173> [artiq] hartytp commented on issue #860: A scope trace showing the SPI lines would allow us to eliminate this kind of thing very quickly.... https://github.com/m-labs/artiq/issues/860#issuecomment-354557118

17:18 <GitHub53> [artiq] sbourdeauducq reopened issue #727: remove multiple jesd initialization attempts if not necessary https://github.com/m-labs/artiq/issues/727

17:21 <GitHub127> [artiq] hartytp commented on issue #860: @sbourdeauducq Remind me, what reference frequency are you using for the HMC830? Is it still 100MHz? https://github.com/m-labs/artiq/issues/860#issuecomment-354557463

17:22 <GitHub77> [artiq] sbourdeauducq commented on issue #860: Yes. https://github.com/m-labs/artiq/issues/860#issuecomment-354557498

18:03 <GitHub141> [artiq] hartytp commented on issue #860: https://github.com/m-labs/artiq/blob/fcc438524c38d1ac336aa8d2b857e4c2338705f3/artiq/firmware/libboard_artiq/hmc830_7043.rs#L34... https://github.com/m-labs/artiq/issues/860#issuecomment-354559839

18:05 <travis-ci> batonius/smoltcp#117 (master - d1ac62c : 寧靜): The build passed.

18:05 <travis-ci> Change view : https://github.com/batonius/smoltcp/compare/960b0012a09d...d1ac62c2a2c2

18:05 <travis-ci> Build details : https://travis-ci.org/batonius/smoltcp/builds/323224014

18:06 <GitHub14> [artiq] hartytp commented on issue #860: https://github.com/m-labs/artiq/blob/fcc438524c38d1ac336aa8d2b857e4c2338705f3/artiq/firmware/libboard_artiq/hmc830_7043.rs#L36... https://github.com/m-labs/artiq/issues/860#issuecomment-354559969

19:14 <GitHub180> [artiq] hartytp commented on issue #860: > What is this for? AFAICT, we're running in HMC mode, so the address register is write only, right?... https://github.com/m-labs/artiq/issues/860#issuecomment-354563230

20:22 <GitHub136> [artiq] enjoy-digital commented on issue #860: @hartytp: i'm reusing an initialization sequence from the vendor that is adapted for our case. But yes we can try to set it to 0. https://github.com/m-labs/artiq/issues/860#issuecomment-354566339

20:44 <GitHub84> [artiq] hartytp commented on issue #860: @enjoy-digital Good to know. Where exactly did you get the initialisation sequence from? Copied from eval software? https://github.com/m-labs/artiq/issues/860#issuecomment-354567332

20:48 <GitHub71> [artiq] hartytp commented on issue #860: Weida is double checking the loop filter, charge pump settings etc. https://github.com/m-labs/artiq/issues/860#issuecomment-354567521

20:50 <GitHub104> [artiq] enjoy-digital commented on issue #860: @hartytp: yes from the evaluation software (but don't have the software with me). Review of the settings is welcome! https://github.com/m-labs/artiq/issues/860#issuecomment-354567593

20:52 <GitHub1> [artiq] hartytp commented on issue #860: I see. Did that spit the SPI transactions out into a text file? Do you have a copy of the original (don't have access to a windows PC atm to do this myself). https://github.com/m-labs/artiq/issues/860#issuecomment-354567696

21:04 <GitHub54> [artiq] hartytp commented on issue #860: @sbourdeauducq @enjoy-digital Have you verified that transitions high before SCLK on startup (must not be any glitches during turn on)? This is needed for proper SPI operation?... https://github.com/m-labs/artiq/issues/860#issuecomment-354568256

21:09 <GitHub60> [artiq] enjoy-digital commented on issue #860: @hartytp: what happens on startup should be fine since we are able to communicate with it then. But that would be good yes to do a capture of a spi transaction. (to see if we have the same issue i had with vivado). The spi transactions generated by the gui are described in a text file, but i don't have access to it now. https://github.com/m-labs/artiq/issues/860#issue

22:20 <GitHub101> [artiq] hartytp commented on issue #860: hmm...these chips are just full of undocumented test features. Note in register 6 how you program all the default values, but the data sheet instructs one to program values different to the default in, without any explanation. https://github.com/m-labs/artiq/issues/860#issuecomment-354571616

23:25 <GitHub91> [artiq] hartytp commented on issue #860: CP should be 1.6mA with this loop filter not 2.54mA. Probably not enough to prevent it from locking, but won't help.... https://github.com/m-labs/artiq/issues/860#issuecomment-354574405