sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub102> [sinara] gkasprow pushed 1 new commit to master: https://github.com/m-labs/sinara/commit/49115e78ebbdbe35f7e684cd4b395f83e701ff26
<GitHub102> sinara/master 49115e7 Greg: fixed poly on mid 1
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<travis-ci> m-labs/smoltcp#378 (master - f239e36 : whitequark): The build passed.
<travis-ci> m-labs/smoltcp#379 (master - f58cc4b : whitequark): The build passed.
<bb-m-labs> build #268 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/268
<_florent_> sb0: hmc830 and hmc7043 spi is now working, going to test clock generation, then ad9154 spi and jesd
<sb0> _florent_, great
<sb0> do you have an allaki to look at the rf output?
<_florent_> i have one "AFE_Mezzanine_template v1.0", is it an allaki?
<_florent_> I guess it's that (2 dac out / 2 adc in), but haven't tested it yet
<sb0> does it have a balun?
<sb0> that's pretty much the only component you really need afaik
<_florent_> does it have a balun? : yes
<_florent_> the Test/Template Mezzanine
<GitHub2> [artiq] sbourdeauducq commented on commit 76ddb06: I suggest moving this to the debug level later on. After spiflash is working, then the default logging level is easily changed. https://github.com/m-labs/artiq/commit/76ddb063cf78fad4c4590225cd29952102ea473e#commitcomment-25426533
<bb-m-labs> build #886 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/886
<sb0> _florent_, should be sufficient
<bb-m-labs> build #609 of artiq-win64-test is complete: Warnings [warnings python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/609 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
<bb-m-labs> build #1772 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1772
<sb0> that's the board that heats up with all those resistors that cannot be switched off ...
<sb0> _florent_, by "spi working" you mean the chip gets detected? but you didn't test lock etc.?
<_florent_> sb0: yes, spi reads/writes are working, need to test clocks
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<rjo> sb0: yeah. why not.
<_florent_> sb0: hmc7043 is working correctly (for now i'm bypassing hmc830 and using external dacclk)
<_florent_> sb0: ad9154 spi working and intialized correctly, serdes pll lock is detected correctly (on dac1 that is the only one working on my board)
<_florent_> sb0: now going to test jesd...
<sb0> _florent_, and the 830 is not working?
<sb0> is the DAC not working an understood hardware issue?
<_florent_> sb0: it's probably working, but i want first to do some tests with my sayma_test repo to be sure i have the right hmc830 config
<sb0> ok
<sb0> how are you testing jesd?
<_florent_> sb0: i did some tests when receiving the board but switched to dacclk when we were having troubles
<_florent_> sb0: bist and stpl results will be enough for now
<sb0> ok. feel free to integrate those tests permanently into the firmware (https://github.com/m-labs/artiq/issues/758)
<_florent_> yes, bist --> prbs sorry...
<_florent_> sb0: for the dac that is not working on my board, it's responding to spi, but i've never been able to get the serdes pll to lock
<_florent_> sb0: it's maybe something that could be fixed by greg, but i don't want to break the board while investigating on that.
<sb0> ok
<_florent_> sb0: greg has been able to get the 2 dacs working on his board IIRC
<sb0> rjo, Alexander is suspecting the 4066 capacitive loading on the SPI flash is causing the problems (spiflash core not working and FPGA not configuring). did Greg try booting the FPGA from the flash?
<sb0> "the MMC will not cause any problem" yea good one.
<rjo> sb0: i don't know. i thought (from your issue) only the spi xip was not working but fpga loading was.
<sb0> i opened two issues. basically nothing is working.
<sb0> the reason xip is not working is the flash reads back 0xffff.... (can be found by mapping the spiflash core elsewhere)
<rjo> so Philips -> NXP -> "Nexperia" now?
<rjo> if FPGA boot does not work then the SPI core is not (certainly not the only) the issue.
<rjo> in that case have a look at the bitstream generation options. i.e. try "not quad spi" and slower clock.
<rjo> the switches have ~4-8 pF. i don't see how that's loading significantly
<sb0> can be other things like M pins
<rjo> yes. that as well. iirc those are dip switches. you took a photo.
<GitHub79> [smoltcp] edef1c commented on issue #3: @dlrobertson looks like you're on par with me, have fun I guess https://git.io/vF80t
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<GitHub37> [sinara] marmeladapk pushed 1 new commit to master: https://github.com/m-labs/sinara/commit/d68f399d1ee5bc00753eb0e6260d0f8623e91dbb
<GitHub37> sinara/master d68f399 Paweł: Kasli rev1.0rc1...
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<cjbe> whitequark: I shipped a JGS516 to HK today. I did not ship a DGS-108 as this pushed the shipment to a higher priceband (more than the switch is worth)
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