sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub95> [smoltcp] dlrobertson commented on pull request #72 5682ccf: Good question. Would the conversions typically happen in `Repr::lower` https://git.io/vFgpS
<sb0> if I understand correctly, with 1000base-x, you can loopback the tx pairs into rx pairs just by connecting them together, and the link should establish and transmitted packets should be received?
<rqou> sb0: yes
<travis-ci> [rust-managed] whitequark pushed 1 new commit to master: https://github.com/m-labs/rust-managed/commit/39eab14876281ca6344610af33438cf2fb89331d
<travis-ci> rust-managed/master 39eab14 whitequark: Add an experimental ManagedMap container.
<whitequark> ^ pushed a part of the ARP solution
<travis-ci> m-labs/rust-managed#24 (master - 39eab14 : whitequark): The build passed.
<travis-ci> [rust-managed] whitequark pushed 1 new commit to master: https://github.com/m-labs/rust-managed/commit/a4f43056c1a2b71c7dd41f40b5b318aba9e9f90d
<travis-ci> rust-managed/master a4f4305 whitequark: Add map feature to build matrix.
<travis-ci> m-labs/rust-managed#25 (master - a4f4305 : whitequark): The build passed.
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<sb0> _florent_, is interframe gap respected if the PHY doesn't drive tx.ack high at all times?
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<GitHub136> [artiq] sbourdeauducq commented on issue #837: Switch received and installed between kc705 and main router. https://github.com/m-labs/artiq/issues/837#issuecomment-343404095
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<GitHub54> [misoc] enjoy-digital pushed 1 new commit to master: https://git.io/vF28T
<GitHub54> misoc/master 780b3f5 Florent Kermarrec: core/sdram_phy/kusddrphy: use locally inverted clk_b on iserdese3
<bb-m-labs> build #273 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/273
<GitHub92> [migen] enjoy-digital pushed 1 new commit to master: https://git.io/vF28y
<GitHub92> migen/master 2274a75 Florent Kermarrec: genlib/cdc: remove AsyncResetSynchronizer on gearbox...
<bb-m-labs> build #199 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/199
<GitHub119> [smoltcp] LuoZijun commented on issue #77: okay https://git.io/vF2BC
<GitHub64> [artiq] enjoy-digital pushed 7 new commits to master: https://github.com/m-labs/artiq/compare/5dc131636d84...aff1609a5349
<GitHub64> artiq/master 59be095 Florent Kermarrec: gateware/serwb/kusphy: use locally inverted clk_b on iserdese3
<GitHub64> artiq/master db82b11 Florent Kermarrec: gateware/serwb/core: cleanup and increase fifo depth
<GitHub64> artiq/master 48bfaec Florent Kermarrec: gateware/serwb/phy: remove unnecessary rx_dly_rst (use wrap-around), fix typo & pep8
<_florent_> sb0: i seem to have better results on serwb with this: https://github.com/m-labs/artiq/commit/59be095512462be83c736326c8ed7a7e5240a5e0
<_florent_> sb0: but not sure this is totally fixed now, i'll do more tests later
<_florent_> sb0: in case you want to try, ad9154.rs is not updated to avoid breaking jesd on kc705, you can use this one: https://github.com/m-labs/artiq/commit/59be095512462be83c736326c8ed7a7e5240a5e0
<_florent_> sb0: for interfame gap, this needs to be tested. To be sure you could modify the gap module to handle the ack (for the gap to always be >= minimum gap)
<bb-m-labs> build #889 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/889
<bb-m-labs> build #1775 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1775 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
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<cr1901_modern> rjo: I have two other PRs to make right now (both platforms). One of them depends on the icestorm fixes, but is otherwise ready. Would you object if I made a PR anyway?
<cr1901_modern> (My changes are purely additive and won't conflict w/ the icestorm improvements).
<rjo> cr1901_modern: sure go ahead. in any case, i don't test any of that: you should write unittests. we do run those.
<cr1901_modern> rjo: Tests for what? (I tested that the platform works on my own machine, of course)
<rjo> cr1901_modern: even a test that makes sure the platform and the toolchain don't break would be useful.
<cr1901_modern> That's gonna make travis builds slower b/c it needs to grab yosys and friends, just fyi
<cr1901_modern> s/travis/buildbot
<cr1901_modern> where is my mind today
<cr1901_modern> rjo: "we do run those." This refers to the buildbot, correct?
<rjo> don't run yosys. just write verilog. there are lots of ways that can break already.
<cr1901_modern> Ahh okay, so basically a contrived module that emits verilog for all the currently-supported lattice platforms would be a decent test?
<rjo> doesn't need to be all platforms, just cover as much code as easily possible.
<cr1901_modern> Will do. Just FYI: https://github.com/m-labs/migen/pull/85 2/3... third and last PR should be done soon
<cr1901_modern> (soon == within the week or so)
<whitequark> _florent_: how would you suggest testing for whether interframe gap handling is correct?
<travis-ci> batonius/smoltcp#105 (master - ef4af85 : Dan Robertson): The build passed.
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