01:14 <GitHub92> [smoltcp] dlrobertson commented on issue #3: @edef1c I'll be largely unavailable for two weeks as well. While I am pumped to help with this issue, I'd hate to push you out of contributing to this.... https://git.io/vF4nS

01:40 <sb0> cjbe: probably negligible compared to the costs of that bug.

02:40 <cr1901_modern> rjo: Sorry, I didn't see this until now before updating: https://github.com/m-labs/migen/pull/84#discussion_r148926943 I'll try to impl diamond attrs tonight

03:17 <whitequark> sb0: question about SED

03:17 <whitequark> there's this bug where pre-SED RTIO fails to detect an underflow

03:17 <whitequark> is SED the way forward? if yes, isn't it a waste of time to investigate that?

03:23 <sb0> yes, SED is the way forward

03:24 <sb0> and yes, this problem is low-prio for this reason. i reported it just in case it becomes a serious issue for some artiq-3 users.

03:27 <GitHub78> [smoltcp] whitequark commented on issue #71: I know. Feel free to contribute a macOS port of the hosted components. I do not currently have plans for that.... https://git.io/vF4RB

03:27 <whitequark> ah ok

03:32 <GitHub75> [smoltcp] dlrobertson commented on issue #3: Sounds good. Shouldn't be too hard to feature gate it https://git.io/vF4Ri

03:40 <GitHub106> [smoltcp] dlrobertson opened pull request #72: [WIP] IPv6 basics in wire (master...ipv6) https://git.io/vF40U

03:42 <GitHub121> [smoltcp] whitequark commented on issue #3: What do you mean by "feature gate"? We're in the `0.x.y` version series, I do not provide compatibility guarantees (though I rarely break code), and I'll only accept PRs that I consider of reasonable quality, so there's no harm in exporting those APIs right away. https://git.io/vF40q

03:43 <sb0> _florent_, what are the current problems with the artix7 gtp drtio code?

03:53 <GitHub194> [smoltcp] dlrobertson commented on issue #3: At least in the initial PR is only adding the packed parsers etc. So I just put everything behind `#[cfg(feature = "ipv6")]` and I didn't add it to the `default`. See #72 for details. https://git.io/vF40K

03:55 <GitHub197> [smoltcp] dlrobertson commented on pull request #72 3bbc760: Using this on a `Pad1` option is more or less a user error since it cannot have a payload. I went back and forth on using an `assert(self.opt_type() != ExtOpType::Pad1)`. https://git.io/vF40X

04:03 <GitHub193> [smoltcp] whitequark commented on issue #72: Okay, this is *way* too much code to even discuss, much less merge, in a single PR. Can you please split it into many PRs, and start small? I suggest the following:... https://git.io/vF4EU

04:19 <GitHub165> [smoltcp] whitequark commented on issue #72: > We can go without extension headers.... https://git.io/vF4ED

04:37 <GitHub142> [smoltcp] whitequark commented on pull request #69 58dd8cc: The header field is called "Identification" by the spec, I suggest just `Ident` https://git.io/vF4ua

05:03 <GitHub3> [smoltcp] whitequark commented on pull request #69 58dd8cc: Can you order `icmp` after `raw`? Here and in `set.rs` and in `ref_.rs` https://git.io/vF4zF

05:06 <sb0> ah, interesting there are some Ethernet PHY chips with TBI on the pins

05:06 <sb0> maybe those can be used for small DRTIO devices using cheap FPGAs that don't have transceivers

05:07 <whitequark> TBI?

05:08 <sb0> raw SERDES (10b codes)

06:26 <sb0> the xilinx transceiver garbage, for all its bloat, cannot give you 125MHz GbE clocks (you get 62.5)... they really designed this thing with maximum encumbrance so that it just barely works for every protocol using all sorts of obscure crap IP

06:47 <_florent_> sb0: artix7 gtp: haven't made progress since last discussion, need to cleanup initialization code that has hacks in it (but works) and test with higher linerates.

06:49 <cr1901_modern> _florent_: While you're here: From what I can gather, Lattice Diamond only supports "//synthesis"-style attributes. Is this correct?

06:50 <cr1901_modern> Context, since most of the diamond code is yours: https://github.com/m-labs/migen/pull/84#discussion_r148926943

06:56 <_florent_> cr1901_modern: Diamond is using synplify, but i don't remember how synthesis attributes can be defined with it

06:58 <cr1901_modern> Okay thanks. I'm just gonna make Diamond use the DummyAttrTranslate for now (i.e. the default).

06:58 <cr1901_modern> _florent_: Would you be willing to do me a favor and instantiate a MultiReg w/ diamond and see if synthesis complains?

06:58 <cr1901_modern> Or anything with an (* attribute = "true" *)

07:39 <_florent_> cr1901_modern: ok I'll test that

07:43 <_florent_> cr1901_modern: just tested on a machxo3 design i have, (* attribute = "true" *) attributes are recognized by the tool

08:57 <cjbe__> sb0: what I meant is that if you need one, I will have a new one sent to you

08:58 <sb0> cjbe__, please make sure that whatever you send us does trigger the bug. consumer hardware often has multiple hardware revisions that are not distinguishable by model number or external appearance.

08:59 <whitequark> these hardware revisions are almost always stated on the packaging though

08:59 <whitequark> at least, every router i touched had them stated

09:39 <sb0> rjo, we can simply use a sayma rtm to test the 1000base-x phy

09:39 <sb0> there are sata connectors that go to the transceivers

09:40 <sb0> put a 125M oscillator into OSC2 or program the si5324

09:59 <_florent_> sb0: it seems i just got jesd working at 5gbps with artiq...

10:01 <sb0> _florent_, good. but why 5?

10:01 <_florent_> sb0: i did a first test at 5gbps to be sure, not going to test more

10:01 <sb0> _florent_, the clocking code should be for 6 gbps

10:02 <sb0> https://github.com/m-labs/artiq/issues/793

10:04 <_florent_> yes i just wanted to test with artiq something i already validated with my sayma_test repo

10:04 <_florent_> i'm going to test 6gbps with sayma_test first, then integrate that in artiq

10:06 <sb0> _florent_, for testing the two DACs you can use the Sayma on our buildserver

10:06 <sb0> sayma1 and sayma3 (see developer notes) have rtms

10:07 <sb0> sayma3 has an additional ddr3 bug

10:08 <_florent_> sb0: ok i'll see, for ddr3 i'm able to reproduce the problem here too

10:09 <_florent_> sb0:; btw for ddr3 on sayma1 / sayma3, where you using the 64 bits of the ddr3 or only 32 as i'm doing here?

10:09 <sb0> 32. 64 always fails.

10:11 <_florent_> ok

10:48 <cr1901_modern> _florent_: Okay tyvm... I just kept the DummyAttrTranslate for diamond for now. It was the default before the PR, and should work fine for the time being.

12:57 <GitHub190> [smoltcp] dlrobertson commented on pull request #69 58dd8cc: What about `Udp`? Since you're binding to ICMP `DstUnreachables` for UDP packets from the given port. https://git.io/vFBk8

12:57 <GitHub6> [smoltcp] dlrobertson commented on pull request #69 58dd8cc: I'm okay with `Ip` though.. just trying to think about how to make this as readable as possible https://git.io/vFBkz

13:07 <_florent_> sb0: i got 6gbps working with my sayma_test repo, now going to test with hmc830 and 100Mhz input clock.

13:30 <sb0> _florent_, ok

13:30 <sb0> _florent_, what happens when a liteeth phy does not drive its sink ack signal high?

13:31 <_florent_> sb0: the core should handle it and freeze things

13:32 <sb0> _florent_, where is that used?

13:38 <_florent_> sb0: it's probably not used since phy are already ready to transmit

13:39 <_florent_> sb0: or maybe used if there is a fifo inside the phy

13:39 <bb-m-labs> build #269 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/269

13:44 <GitHub160> [misoc] sbourdeauducq pushed 1 new commit to master: https://git.io/vFBmr

13:44 <GitHub160> misoc/master d040d0e Sebastien Bourdeauducq: liteeth: use proper python syntax for sets

13:46 <bb-m-labs> build #270 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/270

13:50 <sb0> rjo, gearbox is a bit better, then you need only one 8b10b encoder etc.

16:09 <bb-m-labs> build #271 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/271