00:20 <hartytp_> sb0: no 1V8 issues so far after a couple of days worth of work and quite a few restarts

00:20 <hartytp_> The only difference I can see from your setup is that I haven't updated the MMC firmware (still using whatever Greg originally loaded onto my board).

00:21 <hartytp_> AFAICT, none of Greg, Joe or I see this issue. So seems to be some issue with your setup or your boards (maybe Greg is right and they are damaged, but that seems a bit unlikely)

00:21 <hartytp_> Ideally, it would be great if you could stick a scope on your supply rails

00:22 <hartytp_> otherwise, it would be good if you could post photos of your setup and part numbers for PSUs etc, then post one of your boards back to Greg for further tests

00:22 <hartytp_> I don't recall seeing any serwb issues, no

00:23 <hartytp_> ack on the si5324, although I do remember you having some frustrations getting that up and running. In any case, it's still quite possible that we're doing something daft with the HMC830

00:24 <hartytp_> As I said on GitHub I still have a few ideas for things to look at on that chip. Otherwise, I have an eval board on order, so will use that as a test setup to validate loop filter, register values, etc

00:25 <hartytp_> Did you try altering the muxes to allow you to use an external clock?

00:25 <hartytp_> Ideally, I'd like to work on the HMC830 on Monday (although, can't work on it all day, as have some other lab stuff to do) but if you have problems getting an external clock to work then I can prioritise looking at that instead

00:26 <hartytp_> just let me know what would be most helpful

04:11 <whitequark> rjo: sb0: wanted to say that I'm renaming the lockfiles and ttyUSB*s to be more consistent for sayma and kc705

04:42 <ohsix> whitequark: mitm' with wine; https://paste.ubuntu.com/26382553/ have most of the structure just need to fill it out

04:46 <davidc__> key2: I'd readback the flash after each test

04:48 <whitequark> ohsix: thanks

04:48 <ohsix> it seems to run the same sequence regardless of vendor so it's turning out as a good way to go

04:49 <ohsix> i dunno what i was going to actually tell you to help, but i can talk about what i've done trying to figure it out later :D

12:56 <sb0> hartytp, yes I changed the switches. I'm unsure of my rf generator though (the synthnv firmware is buggy and I don't have something to measure 1.2GHz)

15:16 <rjo> whitequark: ack. good. the developer notes are still appLicable?

15:32 <sb0> so... I wanted to compare the simulation results of the xilinx transceiver trash between my code and the wizard-generated one

15:33 <sb0> but of course that could not go well either: the wizard breaks when you disable the 8b10b encoder

15:36 <sb0> also the wizard has this funny option "Extend reset to 3ms" with this tooltip "Use in case of fast programming modes like BPI and PCAP"

15:37 <sb0> i.e. the xilinx trash works differently depending on how fast you load the bistreams

15:45 <sb0> I might be overly optimistic in assuming that the silicon works without bug with 8b10b disabled...

15:50 <sb0> rjo, what happened to the kasli uart?

17:14 <rjo> sb0: oh. i tried something. let me fix that.

17:16 <rjo> sb0: they are back

17:18 <larsc> sb0: freenode has a bot that k-lines those spambots when it sees them, you can get the bot to join the channel by inviting it the bots name is Sigyn

17:23 <rjo> larsc, sb0: thanks! that would be great.

19:34 <hartytp_> sb0: what happened with your signal generator?

19:35 <hartytp_> so, to be clear, you do want me to look at using an external clock in my setup before doing more work on the HMC830?

19:35 <hartytp_> So, I'll change the mux settings and rebuild the code

19:36 <hartytp_> then inject a 1.2GHz clock into the SMP where the clock mezzanine is supposed to go (IIRC, the LTC chips don't go to 1GHz so I can't use the SMA)

19:36 <hartytp_> I'll 50R terminate the other SMP port

19:37 <hartytp_> __florent__ just to double check, please can you confirm the mux settings required to use the clock mezzanine DAC clock port?

19:37 <hartytp_> then, I'll comment out the HMC830 init code, so that it all starts

19:37 <hartytp_> I'll probe the board to ensure that a 1.2GHz DAC clock is present at the output of the HMC7043 and hence reaching the DACs

19:37 <hartytp_> What will I see if it's working?

19:38 <hartytp_> A message on the UART?

19:38 <hartytp_> and, a ramp on the DAC output, right?

19:38 <hartytp_> anything else I should do/look out for while doing that?

19:38 <hartytp_> ...

19:38 <hartytp_> on another note, can you confirm how the clocking works atm?

19:39 <hartytp_> The DACs are clocked from the 7043, a divided-down version is also sent to the FPGA.

19:39 <hartytp_> Is the JSED core/SAWG/ramp generator clocked from this divided-down version of the DAC clock (from the 7043)?

19:40 <hartytp_> i.e. I'm currently only supplying a single 100MHz clock (soon to be 1.2GHz) so want to check I understand how the FPGA clock ends up phase locked to this.