<sb0>
whitequark, the allaki has a RF attenuator on it with a serial interface (see schematics in the sinara repository)
<sb0>
for the first version we want to program it with a fixed value. it is currently on a GPIO core on the RTM FPGA, accessible over serwb
<sb0>
whitequark, so the runtime should toggle those GPIO pins at startup to set a reasonable attenuation value.
<sb0>
for the hardware test, there is sayma1 with an allaki in the first slot, with the outputs connected to the scope. with a lot of luck, there might be RF output (with the ramp generator that Robert added) after the attenuator is set ...
<bb-m-labs>
build #1917 of artiq is complete: Exception [exception interrupted conda_remove] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1917 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<sb0>
bb-m-labs, force build artiq
<bb-m-labs>
build forced [ETA 42m18s]
<bb-m-labs>
I'll give a shout when the build finishes
<bb-m-labs>
I'll give a shout when the build finishes
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<sb0>
rjo, right now, the ethernet phy works when the transceiver is in PCS loopback mode, and breaks in the same way (rx_data stuck at either 0 or 0x7805c) with PMA loopback or regular connection to the switch
<sb0>
transceiver TX cannot be tested at the moment unless your switch has some advanced diagnostic modes
<sb0>
_florent_, do you remember any special parameters that have to be set or other xilinx rigmaroles we have to follow through when the rx buffer is used?
<sb0>
does the PCS loopback involve the rx buffer?
<GitHub61>
[smoltcp] phil-opp commented on issue #94: > Having to proxy poll_at and egress through the PacketFilter trait should have been enough of an indication for me that this is trying to cut the abstractions that aren't really suited for this.... https://github.com/m-labs/smoltcp/pull/94#issuecomment-356320931
<GitHub181>
[smoltcp] whitequark commented on issue #94: > For example, imagine a custom packet processor that immediately reacts to certain UDP control messages and passes all other packets to an internal SocketSet.... https://github.com/m-labs/smoltcp/pull/94#issuecomment-356322141
<_florent_>
sb0: just curious, what are you using for powering the boards?
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<sb0>
rjo, ping
<sb0>
_florent_, PC ATX power supply and (60A switching) lab power supply.
<sb0>
1v8 problem is present in both cases
<_florent_>
ok
<sb0>
right now they're on the ATX, since it's easier to power-cycle, the lab one was just for testing and seeing if it made a difference for the 1v8 bug
<_florent_>
hmm, it seems sayma1 is only working less than a minute correctly after power up...
<_florent_>
is it expected?
<sb0>
it's quite random, sometimes it crap out at startup, sometimes after seconds, sometimes after hours
<_florent_>
sb0: do you know if the update you did can have impact board behaviour? because i seems more difficult than before to do something with the boards...
<sb0>
_florent_, I only updated sayma2, did not touch sayma1
<sb0>
and yes, those random board failures are a PITA
<_florent_>
i'm wondering is serwb issue and 1.8v issue could be related...
<_florent_>
is/if
<sb0>
the main difference I see with Greg's board is the big input voltage drop
<sb0>
the exar chip reports 11.20V instead of 12V on Greg's board
<sb0>
could be shitty cables, which I used both with the lab PSU and the ATX PSU
<_florent_>
is there a way for me to get this info with my board?
<_florent_>
just to see if i also have the voltage drop or not
<sb0>
reflashing it with the new MMC firmware...
<sb0>
I'm not in the lab anymore
<sb0>
for the one you have at your place, do you have a ARM-JTAG cable with the 10-pin connector?
<bb-m-labs>
build #1920 of artiq is complete: Failure [failed python_coverage_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1920 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
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<GitHub185>
[sinara] gkasprow pushed 1 new commit to master: https://git.io/vNmZJ