01:08 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1166: Is there an older version where that did not happen? https://github.com/m-labs/artiq/issues/1166#issuecomment-427534529

01:32 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1167: > Beyond this (supposedly fixed) bug are there any general objections to using Intel, or is this indicative of the general state of their silicon?... https://github.com/m-labs/artiq/issues/1167#issuecomment-427536159

08:13 <GitHub-m-labs> [artiq] hartytp commented on issue #1167: ASICS are fun. More than cost, my worry would be the difficulty in adding new features or fixing bugs, which would then require hardware modifications. https://github.com/m-labs/artiq/issues/1167#issuecomment-427555735

08:53 <GitHub-m-labs> [artiq] hartytp commented on issue #1166: > Is there an older version where that did not happen?... https://github.com/m-labs/artiq/issues/1166#issuecomment-427557887

11:16 <GitHub-m-labs> [artiq] gkasprow commented on issue #1167: In our scale of the project, it's cheaper and easier to take higher grade FPGA than playing with ASICs.... https://github.com/m-labs/artiq/issues/1167#issuecomment-427565858

12:03 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1167: No matter what grade of FPGA you take, you cannot put megabytes of SRAM into a CPU pipeline running close to a GHz. https://github.com/m-labs/artiq/issues/1167#issuecomment-427568548

12:05 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1167: No matter what grade of FPGA you take, you cannot put megabytes of SRAM into a CPU pipeline running close to a GHz.... https://github.com/m-labs/artiq/issues/1167#issuecomment-427568548

12:38 <GitHub-m-labs> [artiq] gkasprow commented on issue #1167: That's true. But how ASIC would help here? The same logics can be implemented with ASIC and FPGA, Of course FPGA adds sth like 50% of performance penalty. https://github.com/m-labs/artiq/issues/1167#issuecomment-427570466

12:40 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1167: It's more like >90% performance penalty with this kind of thing. Especially with a large RAM that will have to be spread across the whole chip with huge routing delays. https://github.com/m-labs/artiq/issues/1167#issuecomment-427570546

12:40 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1167: It's more like >90% performance penalty with this kind of thing. Especially with a large RAM that will have to be spread across the whole chip with huge routing delays, and the requirement for a big FPGA. https://github.com/m-labs/artiq/issues/1167#issuecomment-427570546

12:43 <GitHub-m-labs> [artiq] gkasprow commented on issue #1167: True, multi-stage pipelines add plenty of performance penalty in terms of memory access time. ASICs can mitigate it. The same applies to round-trip delay of JED204B https://github.com/m-labs/artiq/issues/1167#issuecomment-427570703

13:21 <GitHub-m-labs> [artiq] hartytp opened pull request #1168: Zotino: increase delay after register read in init method to avoid un… (master...master) https://github.com/m-labs/artiq/pull/1168

13:45 <GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/9a509e50701d9a1c29590478be2f4ae52ec50b72

13:45 <GitHub-m-labs> artiq/master 9a509e5 hartytp: Zotino: increase delay after register read in init method to avoid underflows

14:19 <bb-m-labs> build #1890 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1890

14:25 <GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1166: Generally lacking time + need to fix the power supply or microTCA. https://github.com/m-labs/artiq/issues/1166#issuecomment-427577740

14:37 <bb-m-labs> build #1891 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1891

14:41 <bb-m-labs> build #2619 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2619

15:05 <hartytp> sb0: If you're in a hurry to put your new urukul v1.3 systems together then there is a cpld release here: https://github.com/hartytp/urukul/releases

15:06 <hartytp> artiq code: https://github.com/hartytp/artiq/

15:06 <hartytp> can't test on hw until monday, then will submit a pr

15:07 <hartytp> I'd hoped to get a pr out on friday, but things took longer than I'd hoped

15:10 <hartytp> rjo: I've aimed to keep that backwards compatible, which is why the ordering in the cfg register is a bit odd. I also haven't incremented the version check in the artiq code to avoid forcing all users to upgrade to the new cpld code

15:10 <hartytp> anyway, if you have any comments on the code then I'm happy to change it

16:38 <GitHub-m-labs> [artiq] gkasprow commented on issue #1166: @sbourdeauducq Is there a way to get access to your MTCA crate?... https://github.com/m-labs/artiq/issues/1166#issuecomment-427587952

16:38 <sb0> hartytp: thanks