<sb0>
rjo: cpld issue I guess, will reflash it today
<GitHub-m-labs>
[artiq] sbourdeauducq commented on pull request #1188 32b0013: They are not used anywhere else in ARTIQ, they are not used by most other Python projects, they are difficult to write, some functions may return different types depending on the context, and annotations are ignored by the interpreter and are (currently at least) not checked automatically. https://github.com/m-labs/artiq/pull/1188#discussion
<GitHub-m-labs>
[artiq] sbourdeauducq commented on pull request #1185 b5a5be4: Sure. But if ``choices`` does not match this test (e.g. due to a typo) then there is a bug, and not raising an exception here will make it more obscure than it should be. Generally, it is good practice to always use the pattern ``if x=A: elif x=B: ... else: raise ValueError`` (short of a case statement in Python) https://github.com/m-labs/a
<bb-m-labs>
build #2667 of artiq is complete: Exception [exception python_unittest_2 board_unlock_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2667 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
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<sb0>
ERROR: test_sync_window (test_ad9910.AD9910Test) ValueError(0): no valid window/delay
<rjo>
sb0: tell me about the length of the ribbon and mmcx cables.
<rjo>
sb0: are they really plugged in all the way? the window on that system is significantly worse than what I see here.
<sb0>
rjo: checking. can I power it down now?
<rjo>
sb0: sure
<sb0>
everything was plugged correctly
<rjo>
i get 6 taps wide windows at validation delay 1. on tester it's only 2 taps wide. a tap is ~75ps. and validation delay 1 means one tap hold margin and setup margin each.
<rjo>
sb0: how long are the cables?
<sb0>
moment, getting the tape
<rjo>
sb0: just eyeball it.
<sb0>
eem 48cm
<sb0>
mmcx 34cm
<rjo>
i'll try with longer cables here.
<sb0>
putting shorter cables now
<sb0>
21cm
<rjo>
just for kicks, which mmcx did you use?
<sb0>
(eem)
<rjo>
... port on kasli
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<sb0>
J1
<sb0>
the coax was also bent at quite a sharp angle next to that connector. i can try replacing the mmcx cable too
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<sb0>
rjo: how are things looking now?
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<rjo>
just as bad.
<rjo>
on the other test system ihave here, i have seen my first sdram timing failure now. T~65C. and it also takes a damn long time to get the gigabit link up. something like 20 seconds after boot. that's with a direct attach cable and i have never seen problems there before.
<bb-m-labs>
build #2668 of artiq is complete: Exception [exception python_unittest_2 board_unlock_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2668 blamelist: Robert J?rdens <rj@quartiq.de>
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<bb-m-labs>
build #2669 of artiq is complete: Exception [exception python_unittest_2 board_unlock_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2669 blamelist: Robert J?rdens <rj@quartiq.de>
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<rjo>
bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=opticlock artiq-board
<bb-m-labs>
build forced [ETA 17m06s]
<bb-m-labs>
I'll give a shout when the build finishes
<rjo>
bb-m-labs: force build --props=package=artiq-board,artiq_target=kasli,artiq_variant=ptb artiq-board
<bb-m-labs>
The build has been queued, I'll give a shout when it starts
<bb-m-labs>
build #2670 of artiq is complete: Exception [exception python_unittest_2 board_unlock_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2670 blamelist: Robert J?rdens <rj@quartiq.de>
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<larsc>
rjo: where do you manufacture your PCBs again?
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<rjo>
larsc: technosystem and creotech in .pl for the Sinara devices so far.
<bb-m-labs>
build #2671 of artiq is complete: Exception [exception python_unittest_2 board_unlock_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2671 blamelist: Robert J?rdens <rj@quartiq.de>
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