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<lkcl> whitequark: interesting. what does the resultant verilog look like?
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<whitequark> lkcl: "s << 2'd3"
<whitequark> er
<whitequark> lkcl: "s <<< 2'd3"
<lkcl> whitequark: <<< is a signed shift
<lkcl> according to this
<lkcl> arithmetic shift
<lkcl> which proooobably meeeeeans.... that the source register s is signed?
<cr1901_modern> migen regs aren't signed by default
<lkcl> hmmm intriguing
<whitequark> <<< fills with zero anyway
<lkcl> migen/sim/core.py is using <<< as the operator
<lkcl> there's no sign ha ha of a "<<" operator
<lkcl> so i bet when s=Signal(max=16) it's ok
<whitequark> yes
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<lkcl> whitequark, try this:
<lkcl> _Operator("<<", [lhs, rhs])
<lkcl> the simulation may break, but verilog generation might work
<whitequark> mm, not set up for that right now, will try next time i can
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<lkcl> it's just self.comb += s.eq(_Operator("<<", s, 0x3)) or something like that
<whitequark> no, I mean, I don't have the testbench handy
<lkcl> i'm looking at migen/fhdl/structure.py
<lkcl> oh ok :)
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