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<hartytp>
rjo: one Kasli seems to have been DOA from TechnoSystem (wouldn't flash, didn't investigate just sent it back to them. may have been damage during shipping)
<hartytp>
the other issue is probably not really a Kasli issue. I found that the core device crashed with the low clock feq and didn't meet timing with the higher clock freq
<hartytp>
(well, not a hw issue)
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<hartytp>
want to test switching on a -3 speed grade first
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<sb0>
hartytp: the unmodified code meets timing; please test that
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<sb0>
I was also using the higher clock frequency to work around the sdram bug
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<hartytp>
sb0: yes, it's possible that the timing errors were due to the handful of EEMs I added to the build
<hartytp>
I can try without for initial testing, but long run it's obviously no use if it only meets timing in setups that are too simple to be of any practical use
<sb0>
hartytp: there are many other configurations where it doesn't meet timing, this doesn't necessarily have to do with drtio. in fact, if it meets timing with the lower frequency, it likely has nothing to do with drtio.
<sb0>
(most of the drtio code is not clocked by the clock that gets lowered)
<GitHub-m-labs>
[artiq] sbourdeauducq commented on issue #1184: ``ControllerDB`` doesn't really need to be a class though, ``set_host_filter`` can be inlined and ``sync_struct_init`` implemented as a bare function. https://github.com/m-labs/artiq/issues/1184#issuecomment-432280986
<bb-m-labs>
build #2642 of artiq is complete: Exception [exception board_unlock_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2642 blamelist: Drew <drewrisinger@users.noreply.github.com>
<GitHub-m-labs>
[artiq] drewrisinger commented on pull request #1181 64d2e00: yes, but I don't when I read the code. And it helps IDE's autocomplete better. And if you ever use `mypy` or `pylint` or some other type checker. https://github.com/m-labs/artiq/pull/1181#discussion_r227527942
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<GitHub-m-labs>
[artiq] drewrisinger commented on pull request #1181 64d2e00: Ok. So what is your recommendation for scope of a single PR? I try to fix any unreadable code that I discover while working on a single task, and it gets wrapped into the PR. This keeps me from making lots of PRs on just documentation/refactoring, and it reduces my workload in writing infinite amounts of PRs. Because fixing code smells and incomp
<GitHub-m-labs>
[artiq] drewrisinger commented on pull request #1181 64d2e00: So how would you phrase it? This is not a helpful comment, and the code has no documentation or docstrings or comments to convey what is actually supposed to be happening. https://github.com/m-labs/artiq/pull/1181#discussion_r227539476
<hartytp>
sb0: sure, that issue is probably not caused by switching
<hartytp>
what is the plan for fixing it?
<hartytp>
on the board I tried it on, switching consistently crashed after a short time with the lower clock frequency
<hartytp>
even if some basic builds work with switching, if any non-trivial build breaks on some boards then it's not really useable and can't be merged with master.
<hartytp>
I would like to test switching on a realistic system to make sure that all works before merging with master, rather than relying on a basic test setup. IME running realistic experiments as test sequences can highlight issues that would otherwise be missed.
<hartytp>
if it helps, I can post the Kasli variant that wasn't working
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<GitHub-m-labs>
[artiq] sbourdeauducq commented on pull request #1181 2047722: They are not used anywhere else in ARTIQ, and are generally not common practice when developing Python programs. https://github.com/m-labs/artiq/pull/1181#discussion_r227604791