sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<_whitenotifier-3> [nmigen] andresdemski commented on issue #151: Question: How to change FIFO clock dommains? - https://git.io/fjXaB
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<_whitenotifier-3> [nmigen] sbourdeauducq commented on issue #148: Operator like .part() that returns a non-overlapping chunk of signal - https://git.io/fjXVv
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<mtrbot-ml> [mattermost] <sb10q> Anyone has particular 19in rack fan trays to recommend?
<mtrbot-ml> [mattermost] <sb10q> For cooling kasli crates
<mtrbot-ml> [mattermost] <sb10q> Joe listed one on the wiki but it's 120V only
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<mtrbot-ml> [mattermost] <sb10q> @hartytp the thermostat seems to have a power supply problem. all LEDs are off with both PoE and the 12V barrel connector
<mtrbot-ml> [mattermost] <sb10q> the board also doesn't fit in its enclosure, but you probably noticed
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<mtrbot-ml> [mattermost] <hartytp> Less are #40
<mtrbot-ml> [mattermost] <hartytp> Leds
<mtrbot-ml> [mattermost] <hartytp> I.e. we forgot to put any on in v1
<mtrbot-ml> [mattermost] <hartytp> Mechanics is known (you can rotate a capacitor onto its side and then squeeze it in if you want)
<mtrbot-ml> [mattermost] <hartytp> Can’t remember if fixed yet
<mtrbot-ml> [mattermost] <hartytp> We use the Schroff dc fans. Expensive but nice. We also have some cheaper ones from amazon. Basically fine but noisy and not great airflow uniformity
<mtrbot-ml> [mattermost] <sb10q> Well the Ethernet LEDs were also off, but maybe the MCU is just not programmed
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<sb0> whitequark: your irclog.whitequark.org ssl certificate expired
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<mtrbot-ml> [mattermost] <hartytp> Yes iirc that board has never been flashed
<_whitenotifier-3> [nmigen] mithro commented on issue #98: Generated Verilog should be more readable - https://git.io/fjX1G
<_whitenotifier-3> [nmigen] whitequark closed pull request #152: lib.fifo: fix typo. - https://git.io/fjX2U
<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fjX1w
<_whitenotifier-3> [m-labs/nmigen] peteut 81e5983 - lib.fifo: fix typo.
<_whitenotifier-3> [nmigen] whitequark commented on issue #151: Question: How to change FIFO clock dommains? - https://git.io/fjX1K
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<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/558946021?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/558946021?utm_source=github_status&utm_medium=notification
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<whitequark> sb0: yes, I fucked up some certbot options. fixed now
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<whitequark> sb0: btw you should not be using #726 on real designs, it definitely generates broken logic in some edge cases
<whitequark> verilog arithmetic rules are a major nightmare and given what i know now i think a lot of verilog omigen produced worked mostly by accident
<whitequark> and because few if any people used signed signals
<whitequark> migen#165 for example
<rjo> i use signed signals extensively
<whitequark> hm, interesting. it's possible that omigen is more defensive about signed signals than i give it credit for.
<whitequark> bottom line is, i've been adjusting yosys' write_verilog to use less intermediate wires, and the verilog fuzzer is finding a lot of really insidious edge cases
<rjo> yes. matches my experience in practice. intermediate wires is the most efficient way to avoid problems with signed signals.
<whitequark> i do know how i should adjust that pass, but it requires some serious reengineering to get it always right, so i won't do it right now
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