sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<_whitenotifier-3> [m-labs/nmigen-boards] sbourdeauducq pushed 1 commit to master [+0/-0/±1] https://git.io/fjKb7
<_whitenotifier-3> [m-labs/nmigen-boards] sbourdeauducq bb3d6d7 - blackice_ii: add missing import
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<_whitenotifier-3> [nmigen] sbourdeauducq commented on issue #116: Should memory read ports use domain="comb" or domain=None instead of synchronous=False? - https://git.io/fjKNM
<_whitenotifier-3> [nmigen] sbourdeauducq reopened issue #116: Should memory read ports use domain="comb" or domain=None instead of synchronous=False? - https://git.io/fjoyb
<_whitenotifier-3> [m-labs/nmigen] sbourdeauducq pushed 1 commit to master [+0/-0/±1] https://git.io/fjKNQ
<_whitenotifier-3> [m-labs/nmigen] sbourdeauducq 9a1048a - lattice_ecp5: fix get_input
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/553552488?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] Success. 80.76% remains the same compared to 0ab215e - https://codecov.io/gh/m-labs/nmigen/commit/9a1048af50aa2f7b8b75260832e8849255190253
<_whitenotifier-3> [nmigen] Success. Coverage not affected when comparing 0ab215e...9a1048a - https://codecov.io/gh/m-labs/nmigen/commit/9a1048af50aa2f7b8b75260832e8849255190253
<sb0> whitequark: is this get_input/output/... architecture going to work with things like transceiver clock buffers on xilinx (e.g. IBUFDS_GTE3)?
<sb0> that's one special case where you don't want any i/o buffer on the pin, and there are probably others
<sb0> transceiver data pins too
<sb0> whitequark: also for PinsB don't you want the inverting logic to be pushed into the design?
<sb0> in many cases it's free when you just modify a LUT contents; adding an inverting LUT that the synthesizer won't touch uses more resources, degrades timing, and potentially causes issues with things like IOB registers or SERDES
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<sb0> whitequark: if there are unused I/Os in a design, they still appear as IB, and this then causes yosys/nextpnr failures
<sb0> ERROR: Cell '$4' cannot be bound to bel 'X38/Y0/PIOB' since it is already bound to cell 'uart_0__rx__io$tr_io'
<sb0> with crappy error messages like this
<sb0> *unused inputs
<sb0> this occurs if you use the uart resource for TX only, for example
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<sb0> hmm there are other bugs. this new way of doing I/O seems to trigger many yosys/nextpnr problems
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<sb0> rjo: did you find projects using rust+lwip?
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<rjo> sb0: iirc whitequark even wrote a rust lwip wrapper and there were people interested in it.
<sb0> the first artiq rust firmware used lwip, yes
<sb0> there were many problems with it (it is unclear how much of that were due to that liteeth packet buffer bug, since iirc there were attempts to copy data which would have masked that bug) and smoltcp started after that
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<rjo[m]> I remember whitequark pointing people to that old code recently.
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<_whitenotifier-3> [nmigen] sbourdeauducq opened issue #123: better names for I/O primitive instances - https://git.io/fj6eF
<whitequark> sb0: regarding IO buffers, if you don't want any IO buffer on the pin, you do something like this:
<whitequark> clk = platform.request("eth_clk", dir="-")
<whitequark> this gives you a raw inout
<whitequark> that definitely needs to be documented better
<whitequark> regarding inverting logic, let me think about it a bit
<_whitenotifier-3> [nmigen] whitequark commented on issue #116: Should memory read ports use domain="comb" or domain=None instead of synchronous=False? - https://git.io/fj6vf
<whitequark> sb0: regarding "ERROR: Cell '$4' cannot be bound to bel" etc, can you add an issue with an MCVE? this shouldn't happen.
<whitequark> as for triggering yosys/nextpnr problems, using inout ports directly triggers even worse problems that are usually silent miscompilations, and is not really an option
<sb0> I get issues even with the simplest designs...
<whitequark> so where is the github issue then?
<sb0> as for the object returned by platform.request(), is it best practice to use it directly in .eq(), or do x.o.eq(...) / ....eq(x.i)
<sb0> forthcoming, i'm looking into the xilinx stuff atm
<whitequark> ok
<whitequark> regarding the returned object, the best practice is using x.o and x.i
<whitequark> anyway, I gave the IOB instantiation code a fair amount of testing and didn't get anything like the yosys/nextpnr errors you show, so there must be something different that I'm missing
<sb0> ok moment I'm nearly done with the xilinx stuff
<_whitenotifier-3> [m-labs/nmigen-boards] sbourdeauducq pushed 1 commit to master [+1/-0/±0] https://git.io/fj6vl
<_whitenotifier-3> [m-labs/nmigen-boards] sbourdeauducq 0bcb609 - add KC705
<_whitenotifier-3> [m-labs/nmigen-boards] sbourdeauducq pushed 1 commit to master [+0/-0/±1] https://git.io/fj6v4
<_whitenotifier-3> [m-labs/nmigen-boards] sbourdeauducq 7dfe0be - kc705: fix openocd command
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<_whitenotifier-3> [nmigen] sbourdeauducq opened issue #124: nextpnr error: Cell cannot be bound to bel since it is already bound - https://git.io/fj6vV
<whitequark> ok, very interesting, looking at it
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<whitequark> sb0: that's just a bug in the board file
<_whitenotifier-3> [m-labs/nmigen-boards] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fj6vX
<_whitenotifier-3> [m-labs/nmigen-boards] whitequark 6e0cc9d - dev.uart: fix typo.
<whitequark> both rx and tx ended up bound to C11.
<whitequark> and for that matter, omigen didn't detect it either.
<whitequark> so let's just add some code to nmigen to detect and handle this case
<_whitenotifier-3> [nmigen] whitequark commented on issue #124: nextpnr error: Cell cannot be bound to bel since it is already bound - https://git.io/fj6vy
<sb0> okay. i have another two nextpnr crashes that seem related to i/o changes, but the repro is large...
<whitequark> file them as is, I have minimization tools
<whitequark> I wrote a bugpoint pass for yosys
<_whitenotifier-3> [nmigen] whitequark opened issue #125: "comb" should not be accepted as a name in ClockDomain(), DomainRenamer(), etc - https://git.io/fj6fe
<_whitenotifier-3> [nmigen] sbourdeauducq commented on issue #125: "comb" should not be accepted as a name in ClockDomain(), DomainRenamer(), etc - https://git.io/fj6fI
<_whitenotifier-3> [nmigen] whitequark commented on issue #125: "comb" should not be accepted as a name in ClockDomain(), DomainRenamer(), etc - https://git.io/fj6fq
<whitequark> sb0: my main argument for read_port(domain="comb") is for symmetry with m.d.comb and m.d["comb"]
<whitequark> I think it would be unnecessarily confusing if we had to teach people that in some contexts, combinatorial domain is called "comb" but in others it is called None with no apparent logic to it
<whitequark> also, if you are writing generic code, maybe you want to do something like: mem.read_port(domain); m.d[domain] += ...
<sb0> ah, right, you changed the syntax
<whitequark> yes
<whitequark> that was actually rjo's idea, but I liked it.
<sb0> I thought m.d.sync was shorthand for m.d.sync.sys like in migen
<whitequark> ah.
<sb0> in that case ok
<_whitenotifier-3> [nmigen] whitequark commented on issue #116: Should memory read ports use domain="comb" or domain=None instead of synchronous=False? - https://git.io/fj6fc
<_whitenotifier-3> [nmigen] whitequark closed issue #116: Should memory read ports use domain="comb" or domain=None instead of synchronous=False? - https://git.io/fjoyb
<whitequark> sb0: I have this idea for an API and I want to know what you think about it
<whitequark> let's say I have an instruction decoder that has a ton of signals as outputs. I want to be able to tap into combinatorial outputs as well as register them, without writing too much code
<whitequark> so the natural thing is to do something like:
<whitequark> self.o = Record([...])
<whitequark> self.r = Record.like(self.o)
<whitequark> self.ce = Signal()
<whitequark> with m.If(self.ce): m.d.sync += self.r.eq(self.o)
<whitequark> the thing is that currently the inner signals in Record can't be created with options. you can't make them reset_less, can't set reset value, can't set the decoder
<whitequark> maybe we should extend Layout to allow that?
<_whitenotifier-3> [nmigen] whitequark opened issue #126: Record.like ignores modifications to signals - https://git.io/fj6fV
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<sb0> whitequark: seems there's some regression in nmigen.compat regarding Case - this started failing https://nixbld.m-labs.hk/build/7917/nixlog/1
<sb0> improving Layout seems fine
<sb0> though sometimes it might be better to overwrite the properties on the signals after the Record has been created?
<whitequark> yes, that already works
<whitequark> (except there is #126 that has unobvious behavior)
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<cr1901_modern1> >sb0: I thought m.d.sync was shorthand for m.d.sync.sys like in migen
<cr1901_modern1> FWIW, this was also not clear to me until it was explained that the shorthand is gone
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<whitequark> sb0: fixed the compat regressions
<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 3 commits to master [+0/-0/±3] https://git.io/fj6T5
<_whitenotifier-3> [m-labs/nmigen] whitequark 9eb8160 - compat.fhdl.structure: fix If/Elif/Else after 32446831.
<_whitenotifier-3> [m-labs/nmigen] whitequark c98b8f7 - compat.fhdl.specials: fix Memory.get_port() after 94e8f479.
<_whitenotifier-3> [m-labs/nmigen] whitequark eeb6aca - compat.fhdl.specials: use "sync" as default domain, not "sys".
<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fj6Tb
<_whitenotifier-3> [m-labs/nmigen] whitequark 668ff40 - compat.fhdl.specials: mark CompatMemory as Elaboratable.
<_whitenotifier-3> [nmigen] Error. The Travis CI build could not complete due to an error - https://travis-ci.org/m-labs/nmigen/builds/553758335?utm_source=github_status&utm_medium=notification
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<sb0> whitequark: thanks
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/553758696?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fj6IR
<_whitenotifier-3> [m-labs/nmigen] whitequark 5800f00 - hdl.rec: accept Record(src_loc_at=...).
<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±4] https://git.io/fj6Ig
<_whitenotifier-3> [m-labs/nmigen] whitequark 33f2162 - vendor: give names to IO buffer instances.
<_whitenotifier-3> [nmigen] whitequark closed issue #123: better names for I/O primitive instances - https://git.io/fj6eF
<_whitenotifier-3> [nmigen] Error. The Travis CI build could not complete due to an error - https://travis-ci.org/m-labs/nmigen/builds/553788447?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] whitequark commented on issue #124: Detect pin/ball conflicts between resources when they are requested - https://git.io/fj6I2
<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fj6IP
<_whitenotifier-3> [m-labs/nmigen] whitequark 7059cb4 - hdl.rec: thread src_loc_at to all inner Signals and Records.
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/553791505?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] Failure. 80.7% (-0.06%) compared to 9a1048a - https://codecov.io/gh/m-labs/nmigen/commit/33f21628bb33f1ab6fa3d9dabe930d2650fe6ea8
<_whitenotifier-3> [nmigen] Success. Coverage not affected when comparing 9a1048a...33f2162 - https://codecov.io/gh/m-labs/nmigen/commit/33f21628bb33f1ab6fa3d9dabe930d2650fe6ea8
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/553794048?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/fj6LI
<_whitenotifier-3> [m-labs/nmigen] whitequark b471e33 - build.res: detect physical conflicts earlier.
<_whitenotifier-3> [nmigen] whitequark closed issue #124: Detect pin/ball conflicts between resources when they are requested - https://git.io/fj6vV
<_whitenotifier-3> [nmigen] whitequark commented on issue #124: Detect pin/ball conflicts between resources when they are requested - https://git.io/fj6Lt
<_whitenotifier-3> [nmigen] Success. 80.7% (+0%) compared to 33f2162 - https://codecov.io/gh/m-labs/nmigen/commit/7059cb49314d63e1d0f2d5ee21c54a701aaa44f8
<_whitenotifier-3> [nmigen] Success. 100% of diff hit (target 80.7%) - https://codecov.io/gh/m-labs/nmigen/commit/7059cb49314d63e1d0f2d5ee21c54a701aaa44f8
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<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/553802783?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] Success. 80.73% (+0.02%) compared to 7059cb4 - https://codecov.io/gh/m-labs/nmigen/commit/b471e33d7f79a2e427c341e1e3fffb8c7a368213
<_whitenotifier-3> [nmigen] Success. 100% of diff hit (target 80.7%) - https://codecov.io/gh/m-labs/nmigen/commit/b471e33d7f79a2e427c341e1e3fffb8c7a368213
<_whitenotifier-3> [nmigen-boards] jfng opened pull request #14: Factor out SPI resource definition. - https://git.io/fj6ty
<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 2 commits to master [+0/-0/±5] https://git.io/fj6tQ
<_whitenotifier-3> [m-labs/nmigen] whitequark e351e27 - hdl.ast: fix src_loc_at for Mux().
<_whitenotifier-3> [m-labs/nmigen] whitequark 82903e4 - back.rtlil: emit \src attributes for processes via Switch and Assign.
<_whitenotifier-3> [m-labs/nmigen-boards] whitequark pushed 1 commit to master [+1/-0/±1] https://git.io/fj6t7
<_whitenotifier-3> [m-labs/nmigen-boards] jfng 8d4d940 - Factor out SPI resource definition.
<_whitenotifier-3> [nmigen-boards] whitequark closed pull request #14: Factor out SPI resource definition. - https://git.io/fj6ty
<_whitenotifier-3> [nmigen-boards] jfng synchronize pull request #4: Add Arty A7 platform. - https://git.io/fjzom
<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fj6tb
<_whitenotifier-3> [m-labs/nmigen] whitequark 2e4cc47 - hdl.dsl: fix src_loc_at for FSM state signal.
<_whitenotifier-3> [nmigen] Error. The Travis CI build could not complete due to an error - https://travis-ci.org/m-labs/nmigen/builds/553835968?utm_source=github_status&utm_medium=notification
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<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/553838385?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] Success. 80.82% (+0.09%) compared to b471e33 - https://codecov.io/gh/m-labs/nmigen/commit/2e4cc47fcb5de1c2f5b64bf060fe87accff90d3c
<_whitenotifier-3> [nmigen] Success. Coverage not affected when comparing b471e33...2e4cc47 - https://codecov.io/gh/m-labs/nmigen/commit/2e4cc47fcb5de1c2f5b64bf060fe87accff90d3c
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