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_whitenotifier-3 >
[m-labs/nmigen] whitequark 29fee01 - hdl.ir: warn if .elaborate() returns None.
12:30
<
_whitenotifier-3 >
[nmigen] whitequark closed pull request #164: Specific error message for missing module return from 'elaborate'. -
https://git.io/fj9wV
13:07
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark bcdc280 - hdl.ast, back.rtlil: add source locations to anonymous wires.
13:07
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 94e13ef - hdl.ast: deprecate Value.part, add Value.{bit,word}_select.
13:07
<
_whitenotifier-3 >
[nmigen] whitequark closed issue #148: Operator like .part() that returns a non-overlapping chunk of signal -
https://git.io/fjXCx
13:15
<
vup >
whitequark: shouldn't the deprecation message say use `.bit_select` and not use `.bit_slip`?
13:20
<
whitequark >
vup: oops
13:21
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 0a603b3 - hdl.ast: fix typo.
13:28
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark ee03eab - back.rtlil: fix sim-synth mismatch with assigns following switches.
13:28
<
_whitenotifier-3 >
[nmigen] whitequark closed issue #155: Simulation-synthesis mismatch overriding value selected in a switch with a plain assignment -
https://git.io/fj1Kf
13:28
<
whitequark >
ok, this was the issue that worried me the most
13:43
<
_whitenotifier-3 >
[nmigen] whitequark commented on issue #159: (~False) instead of (not False) can break a design -
https://git.io/fjHeO
14:00
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark ab5426c - Improve test added in 29fee01f to not leak warnings.
14:00
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark ace2b5f - hdl.dsl: warn on suspicious statements like `m.If(~True):`.
14:00
<
_whitenotifier-3 >
[nmigen] whitequark closed issue #159: (~True) instead of (not True) can break a design -
https://git.io/fjDXP
14:24
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<
_whitenotifier-3 >
[m-labs/nmigen] whitequark fdb0c5a - hdl.ir: call back from Fragment.prepare if a clock domain is missing.
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_whitenotifier-3 >
[m-labs/nmigen] whitequark fc84653 - hdl.ir: raise DomainError if a domain is used but not defined.
15:44
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark cea92e9 - hdl.ir: allow returning elaboratables from missing domain callback.
15:45
<
whitequark >
mkay... the remaining part is the platform stuff
16:19
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 4dbb535 - build.plat: add default_clk{,_constraint,_frequency}.
16:20
<
_whitenotifier-3 >
[m-labs/nmigen-boards] whitequark bc2d42e - Replace subprocess.run(..., check=True) with subprocess.check_call().
16:20
<
_whitenotifier-3 >
[m-labs/nmigen-boards] whitequark d5bea94 - Update all boards to use default_clk.
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16:22
<
whitequark >
sb: are there any special concerns about resetting designs on xilinx devices?
16:22
<
whitequark >
for example, on ice40, BRAMs are not functional for some microseconds after startup
16:23
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whitequark >
(this is of course not documented anywhere...)
16:26
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whitequark >
sb: the crux of the question is: is there any point in generating a power on reset on xilinx? or should the clock domain created automatically by platform for default_clk be just reset_less?
16:28
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 21f2f8c - build.plat: add default_rst, to be used with default_clk.
16:29
<
_whitenotifier-3 >
[m-labs/nmigen-boards] whitequark 84321d8 - Update all boards to use default_rst.
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<
_whitenotifier-3 >
[m-labs/nmigen-boards] whitequark 2cf8599 - Remove explicit domain instantiation from blinky.
18:49
<
whitequark >
cr1901_modern: okay,
*now* you can write/edit/publish (whichever stage you're at) the blog post
18:49
<
whitequark >
i consider clock domain work in nmigen ~finished, at least for 0.1
18:50
<
cr1901_modern >
ack
18:52
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 9c28b61 - hdl.ir: don't expose as ports missing domains added via elaboratables.
18:52
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark e0b54b4 - hdl.ir: allow adding more than one domain in missing domain callback.
18:52
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 8854ca0 - build.plat,vendor: automatically create sync domain from default_clk.
18:52
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 99d2054 - hdl.dsl: reword m.If(~True) warning to be more clear.
18:52
<
_whitenotifier-3 >
[nmigen] whitequark closed issue #57: Fragment.prepare should allow caller to handle nonexistent clock domains -
https://git.io/fjmtP
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22:53
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 0fe0518 - compat.fhdl.specials: track changes in build.plat.
22:53
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 8dd54ac - build.run: use keyword-only arguments where appropriate.
22:59
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 999a2f6 - vendor.lattice_ice40: add missing signal indexing.
23:46
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 578c1c5 - back.rtlil: actually match shape of left hand side.
23:48
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark d0ac8bf - back.rtlil: actually match shape of left hand side.