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[nmigen] codecov[bot] commented on pull request #188: [DRAFT] Allow PULLUP=1 as a valid int attr value to re-enable yosys 0.9 - https://git.io/fjx6n
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[mattermost] <sb10q> @astro so what's the latest status of ionpak-thermostat? Is there anything @hartytp can test?
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[mattermost] <sb10q> Is the PWM set up?
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[mattermost] <sb10q> @astro your ADC data is just as corrupted as the identification register. for example I'm observing the samples 2377873 followed by 2115729. hex(2377873-2115729) = 0x40000
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[mattermost] <sb10q> this is digital corruption and not analog noise
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[mattermost] <sb10q> the weird thing is, it's a 1 that appeared in the middle of 0's, so this doesn't look like a timing problem
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[mattermost] <sb10q> (unless the ADC is clocked too fast and breaks?)
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[mattermost] <sb10q> and changing the value in delay_fn does all sorts of weird things...
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[m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/fjx1Z
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[m-labs/nmigen] whitequark a4b58cb - build.dsl: allow both str and int resource attributes.
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[nmigen] whitequark commented on pull request #188: [DRAFT] Allow PULLUP=1 as a valid int attr value to re-enable yosys 0.9 - https://git.io/fjx1C
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[nmigen] whitequark closed pull request #188: [DRAFT] Allow PULLUP=1 as a valid int attr value to re-enable yosys 0.9 - https://git.io/fjx6t
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[m-labs/nmigen-boards] whitequark pushed 5 commits to master [+4/-0/±8] https://git.io/fjx10
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[nmigen] whitequark opened pull request #189: vendor.lattice_ecp5: drive GSR synchronous to user clock by default - https://git.io/fjxDY
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[nmigen] codecov[bot] commented on pull request #189: vendor.lattice_ecp5: drive GSR synchronous to user clock by default - https://git.io/fjxHj
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[nmigen] ret commented on pull request #188: [DRAFT] Allow PULLUP=1 as a valid int attr value to re-enable yosys 0.9 - https://git.io/fjx7j
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[nmigen] dlharmon opened issue #190: platform output bus bits in separate modules causes AssertionError - https://git.io/fjxAu
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[nmigen] whitequark commented on issue #190: platform output bus bits in separate modules causes AssertionError - https://git.io/fjxAV
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[nmigen] whitequark commented on issue #190: platform output bus bits in separate modules causes AssertionError - https://git.io/fjxAw
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[nmigen] emilazy opened pull request #191: {_toolchain,build.plat,vendor.*}: add required_tools list and checks. - https://git.io/fjxAo
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[nmigen] dlharmon commented on issue #190: platform output bus bits in separate modules causes AssertionError - https://git.io/fjxA6
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[nmigen] whitequark closed pull request #191: {_toolchain,build.plat,vendor.*}: add required_tools list and checks. - https://git.io/fjxAo
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[m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±8] https://git.io/fjxAi
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[m-labs/nmigen] emilazy e31a95f - _toolchain,build.plat,vendor.*: add required_tools list and checks.
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[nmigen] whitequark commented on issue #190: platform output bus bits in separate modules causes AssertionError - https://git.io/fjxAP
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[nmigen] whitequark commented on issue #190: platform output bus bits in separate modules causes AssertionError - https://git.io/fjxA1
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[nmigen] dlharmon commented on issue #190: platform output bus bits in separate modules causes AssertionError - https://git.io/fjxAy
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[nmigen] whitequark commented on issue #190: platform output bus bits in separate modules causes AssertionError - https://git.io/fjxAS