sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<mtrbot-ml> [mattermost] <dgy> I don,t know how to solve the problem because I am not good at computer,who can help me?UnsatisfiableError: The following specifications were found to be incompatible with each other:
<mtrbot-ml> [mattermost] <dgy> Package sphinxcontrib-wavedrom conflicts for:
<mtrbot-ml> [mattermost] <dgy> artiq -> sphinxcontrib-wavedrom
<mtrbot-ml> [mattermost] <dgy> Package h5py conflicts for:
<mtrbot-ml> [mattermost] <dgy> artiq -> h5py=2.8
<mtrbot-ml> [mattermost] <dgy> Package openocd conflicts for:
<mtrbot-ml> [mattermost] <dgy> artiq -> openocd[version='0.10.0|>=0.10',build='6|1']
<mtrbot-ml> [mattermost] <dgy> Package pyqt5 conflicts for:
<mtrbot-ml> [mattermost] <dgy> artiq -> pyqt5
<mtrbot-ml> [mattermost] <dgy> Package levenshtein conflicts for:
<mtrbot-ml> [mattermost] <dgy> artiq -> levenshtein
<mtrbot-ml> [mattermost] <dgy> Package lit conflicts for:
<mtrbot-ml> [mattermost] <dgy> artiq -> lit
<mtrbot-ml> [mattermost] <dgy> Package numpy conflicts for:
<mtrbot-ml> [mattermost] <dgy> artiq -> numpy
<mtrbot-ml> [mattermost] <dgy> Package pyqt conflicts for:
<mtrbot-ml> [mattermost] <dgy> artiq -> pyqt[version='>=5.5']
<mtrbot-ml> [mattermost] <dgy> Package scipy conflicts for:
<mtrbot-ml> [mattermost] <dgy> artiq -> scipy
<mtrbot-ml> [mattermost] <dgy> Package binutils-or1k-linux conflicts for:
<mtrbot-ml> [mattermost] <dgy> artiq -> binutils-or1k-linux[version='>=2.27']
<mtrbot-ml> [mattermost] <dgy> Package sphinx conflicts for:
<mtrbot-ml> [mattermost] <dgy> artiq -> sphinx==1.4.8
<mtrbot-ml> [mattermost] <dgy> Package outputcheck conflicts for:
<mtrbot-ml> [mattermost] <dgy> artiq -> outputcheck
<mtrbot-ml> [mattermost] <dgy> Package python-dateutil conflicts for:
<mtrbot-ml> [mattermost] <dgy> artiq -> python-dateutil
<mtrbot-ml> [mattermost] <dgy> Package sphinx_rtd_theme conflicts for:
<mtrbot-ml> [mattermost] <dgy> artiq -> sphinx_rtd_theme
<mtrbot-ml> [mattermost] <dgy> Package dateutil conflicts for:
<mtrbot-ml> [mattermost] <dgy> artiq -> dateutil <message clipped>
<lkcl> very weird behaviour, occurred twice now, so i sort-of have a handle on it.
<whitequark> lkcl: pysim has a number of bugs that need to be fixed, yes.
<whitequark> probably via some medium scale rework.
<lkcl> okaay.
<lkcl> ok so it's a known issue.
<lkcl> that's fine :)
<whitequark> not this specific one
<whitequark> but yes, it's an area i expect bugs in
<lkcl> ok
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<whitequark> sb0: see irc above
<whitequark> and this should be a bug on github anyway.
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<_whitenotifier-3> [nmigen] whitequark opened issue #172: AsyncFIFO/AsyncFIFOBuffered do not infer BRAMs on iCE40 - https://git.io/fjFcp
<_whitenotifier-3> [nmigen] whitequark commented on issue #172: AsyncFIFO/AsyncFIFOBuffered do not infer BRAMs on iCE40 - https://git.io/fjFCf
<whitequark> huh, AsyncFIFO* are broken
<cr1901_modern> I was under the impression AsyncFIFO was never going to infer BRAMs on ice40 b/c no dist RAM
<cr1901_modern> FWIW, I also had a working AsyncFIFOBuffered design on ice40up5k for a soft core when I got icebreaker micropython to work in LiteX (sic!).
<whitequark> what
<whitequark> how is LUTRAM related to this
<cr1901_modern> (10:04:47 AM) cr1901_modern: I was under the impression AsyncFIFO was never going to infer BRAMs on ice40 b/c no dist RAM <-- misspoke
<cr1901_modern> nevermind.
<cr1901_modern> Actually, no I don't think I misspoke. I've had ice40 designs where yosys decided to but the entire AsyncFIFO into LUTs (eating about 20% of my LUTs)! Using an AsyncFIFOBuffered fixed this. But I don't remember why b/c this was like December 2018.
<whitequark> it's explained in the issue
<whitequark> AsyncFIFOBuffered doesn't help anymore
<cr1901_modern> >It was probably a bug in Yosys that allowed it before. <-- But my design _worked_ when BRAM was used. Maybe a lucky accident?
<cr1901_modern> And this was a SoC/soft core, utilizing 90% of the up5k, not some 50 line minimal design.
<whitequark> hm
<whitequark> interesting
* cr1901_modern takes a quick look for his PR/and logs
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<cr1901_modern> Can't find it in Github PRs... it's somewhere in mithro's/timvideos logs. I will look in a bit.
<whitequark> ok, so if it infers LUTs, that's ok
<whitequark> but it still infers LUTs with AsyncFIFOBuffered when i tested it just now
<whitequark> for reasons i haven't closely looked at
<cr1901_modern> I _know_ you already considered this, but... how big was your FIFO? Would yosys have thought it too small to bother putting into BRAM?
<cr1901_modern> Anyways, it could've been an accident that my design worked at all. Just wanted to add it as a data point (perhaps as a "bisect good")
<whitequark> 512 bytes
<whitequark> and it fails PNR
<_whitenotifier-3> [nmigen] whitequark opened issue #173: Platform function to calculate optimal BRAM depth for width - https://git.io/fjFCb
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<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 2 commits to master [+0/-0/±2] https://git.io/fjF8y
<_whitenotifier-3> [m-labs/nmigen] whitequark d44ea4e - hdl.xfrm: make deprecated CEInserter more well-behaved.
<_whitenotifier-3> [m-labs/nmigen] whitequark 84f2c3d - compat.fhdl.decorators: avoid using deprecated NativeCEInserter.
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/573460196?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] Success. 80.56% (+0.15%) compared to ed7e07c - https://codecov.io/gh/m-labs/nmigen/commit/84f2c3df2bfec2fd7eeb30c5567562cc303fbde2
<_whitenotifier-3> [nmigen] Success. 100% of diff hit (target 80.41%) - https://codecov.io/gh/m-labs/nmigen/commit/84f2c3df2bfec2fd7eeb30c5567562cc303fbde2
<_whitenotifier-3> [nmigen] Success. 80.41% (+0%) compared to ed7e07c - https://codecov.io/gh/m-labs/nmigen/commit/84f2c3df2bfec2fd7eeb30c5567562cc303fbde2
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/573460196?utm_source=github_status&utm_medium=notification
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<_whitenotifier-3> [smoltcp] crawford commented on issue #223: Unable to create UDP and TCP sockets - https://git.io/fjF4m
<_whitenotifier-3> [smoltcp] crawford closed issue #223: Unable to create UDP and TCP sockets - https://git.io/fjF4Y
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<vup> whitequark: is it possible to nest connectors in nmigen?
<whitequark> you can specify a connector pin that's from another connector yes
<vup> how?
<whitequark> if you have Connector("X", 1, "A1") then use "X_1:1" in a new one
<whitequark> that will then map to ball A1.
<vup> great, thanks
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<vup> whitequark: what do you think about adding a 'conn=' argument to Connector?
<whitequark> sure. feel free.
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<_whitenotifier-3> [nmigen] rroohhh opened pull request #174: add conn argument to Connector - https://git.io/fjFRL
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/573503224?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] codecov[bot] commented on pull request #174: add conn argument to Connector - https://git.io/fjFRY
<_whitenotifier-3> [nmigen] Success. Absolute coverage decreased by -0.01% but relative coverage increased by +1.4% compared to 84f2c3d - https://codecov.io/gh/m-labs/nmigen/compare/84f2c3df2bfec2fd7eeb30c5567562cc303fbde2...3ff663d5cb4eb1930a203efd73315f24de17f05b
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/573503224?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] whitequark synchronize pull request #174: add conn argument to Connector - https://git.io/fjFRL
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/573504086?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] Success. Absolute coverage decreased by -0.01% but relative coverage increased by +1.4% compared to 84f2c3d - https://codecov.io/gh/m-labs/nmigen/compare/84f2c3df2bfec2fd7eeb30c5567562cc303fbde2...118ea1ebee507e6bd1b053c25e17b435728161cf
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/573504086?utm_source=github_status&utm_medium=notification
<cr1901_modern> this is the nested connectors feature?
<vup> it just makes it easier to write nested connectors
<cr1901_modern> How was it done before this commit?
<cr1901_modern> And are both ways to write nested connectors still present?
<vup> if you had a Connector("con", 0, "A1") you could chain a second connectors using Connector("con_nested", 0, "con_0:1")
<vup> now you can wirte Connector("con_nested", 0, "1", conn=("con", 0))
<cr1901_modern> oh cool
<cr1901_modern> There's a few things in nmigen where "there's more than one way to accomplish the same goal". I try to keep track of them.
<cr1901_modern> But I missed this one lol
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<_whitenotifier-3> [nmigen] whitequark closed pull request #174: add conn argument to Connector - https://git.io/fjFRL
<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±3] https://git.io/fjFRo
<_whitenotifier-3> [m-labs/nmigen] rroohhh 8e048c5 - build.dsl: add conn argument to Connector.
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/573511199?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] Success. Absolute coverage decreased by -0.01% but relative coverage increased by +1.4% compared to 84f2c3d - https://codecov.io/gh/m-labs/nmigen/commit/8e048c5a7ce0f6ca2c4ccebd64361a1029aa9637
<_whitenotifier-3> [nmigen] Success. 81.81% of diff hit (target 80.41%) - https://codecov.io/gh/m-labs/nmigen/commit/8e048c5a7ce0f6ca2c4ccebd64361a1029aa9637
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<anuejn> whitequark: how do you feel about having a function, that adds both connectors and resources from a mixed list?
<anuejn> or is there already one?
<whitequark> doesn't seem very appropriate to me
<anuejn> e.g. when you have an extention board that you want to connect to an SOM
<whitequark> hmm
<whitequark> i mean calling 2 functions instead of 1 doesn't seem like a huge effort
<anuejn> yup but then you wouldnt be able to represent the whole extention board as one thing
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<anuejn> (or would have to employ some filter hack)
<whitequark> wouldn't it be like a function anyway?
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<whitequark> def extend_with_your_board(platform): etc
<whitequark> it's usually a function anyway because it's parameterizable
<anuejn> ah i see
<anuejn> yes that makes sense
<anuejn> tx
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<Astro-> wow!
<Astro-> @sb10q I receive ethernet packets from the cora
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<Astro-> I passed my mhz as hz in the clock setup -_-
<Astro-> this would have been avoidable had I used types like they do in https://github.com/stm32-rs/stm32f4xx-hal/blob/master/src/time.rs
<_whitenotifier-3> [nmigen-boards] rroohhh opened pull request #27: add zturn lite board - https://git.io/fjF0D
<_whitenotifier-3> [nmigen-boards] whitequark commented on pull request #27: add zturn lite board - https://git.io/fjF0y
<_whitenotifier-3> [nmigen-boards] whitequark reviewed pull request #27 commit - https://git.io/fjF0S
<_whitenotifier-3> [nmigen-boards] rroohhh reviewed pull request #27 commit - https://git.io/fjF0N
<_whitenotifier-3> [nmigen-boards] whitequark reviewed pull request #27 commit - https://git.io/fjF0x
<_whitenotifier-3> [nmigen-boards] rroohhh synchronize pull request #27: add zturn lite board - https://git.io/fjF0D
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