01:13 <zignig> whitequark: thanks , <not> That's a bit obsucure and obfuscated </not>.

01:14 <whitequark> huh? it's completely standard Python code

01:14 <whitequark> like i'm just doing the recommended thing

01:14 <zignig> whitequark: sarcasm, sorryt does not come over IRC well ;)

01:16 <zignig> had a bash last night, https://github.com/zignig/Boneless-CPU/tree/change_to_class

01:17 <whitequark> you're probably better off stating what kind of features you want rather than just implementing them

01:21 <whitequark> i don't really believe in "organic growth". if a feature is added it should have clear purpose and design

01:21 <whitequark> code is secondary

01:22 <zignig> ok. I'll annotate my work so far and pose some features.

06:49 <_whitenotifier-3> [nmigen] sbourdeauducq opened issue #153: support for memories with N read-only ports + 1 write-only port? - https://git.io/fj137

06:51 <_whitenotifier-3> [nmigen] whitequark commented on issue #153: support for memories with N read-only ports + 1 write-only port? - https://git.io/fj13d

11:30 <cr1901_modern1> Frome experience, ISE and Vivado already do the block RAM dup trick for lm32, at least from Verilog: https://github.com/m-labs/lm32/blob/84b3e3ca0ad9535acaef201c1482342871358b08/rtl/lm32_cpu.v#L1506

11:33 <_whitenotifier-3> [nmigen] Fatsie opened issue #154: CEInserter does not work on memory ports - https://git.io/fj1Cy

16:06 <_whitenotifier-3> [nmigen] whitequark commented on issue #154: CEInserter does not work on memory ports - https://git.io/fj1R9