01:22 <mtrbot-ml> [mattermost] <sb10q> @rjo your new kasli variant does not compile

01:23 <mtrbot-ml> [mattermost] <sb10q> https://nixbld.m-labs.hk/build/10158/nixlog/1

02:15 <mtrbot-ml> [mattermost] <sb10q> @rjo I've partially set up HTTP/2 server push (which is more complicated than I thought) on the main page (https://m-labs.hk/) - is that improving things for you?

02:15 <mtrbot-ml> [mattermost] <sb10q> if so I'll set it up further

02:20 <mtrbot-ml> [mattermost] <sb10q> ah, I can just run nghttp on the quartiq machine, that works well and demonstrates the issue

02:26 <mtrbot-ml> [mattermost] <sb10q> should be >2x faster now when uncached...

02:49 <mtrbot-ml> [mattermost] <sb10q> hmm

02:49 <mtrbot-ml> [mattermost] <sb10q> there are other issues

04:44 <_whitenotifier-3> [smoltcp] whitequark edited pull request #279: tcp: mitigate illegal state transitions on simultaneous close - https://git.io/fjS7k

04:58 <_whitenotifier-3> [nmigen] whitequark commented on issue #98: Generated Verilog should be more readable - https://git.io/fjS73

05:19 <_whitenotifier-3> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±3] https://git.io/fjS7z

05:19 <_whitenotifier-3> [m-labs/nmigen] whitequark 29a741d - hdl.xfrm: handle mem.{Read,Write}Port in CEInserter.

05:19 <_whitenotifier-3> [nmigen] whitequark closed issue #148: Operator like .part() that returns a non-overlapping chunk of signal - https://git.io/fjXCx

05:20 <_whitenotifier-3> [nmigen] whitequark reopened issue #148: Operator like .part() that returns a non-overlapping chunk of signal - https://git.io/fjXCx

05:20 <_whitenotifier-3> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±3] https://git.io/fjS7g

05:20 <_whitenotifier-3> [m-labs/nmigen] whitequark 995e4ad - hdl.xfrm: handle mem.{Read,Write}Port in CEInserter.

05:20 <_whitenotifier-3> [nmigen] whitequark closed issue #154: CEInserter does not work on memory ports - https://git.io/fj1Cy

05:20 <_whitenotifier-3> [nmigen] Error. The Travis CI build could not complete due to an error - https://travis-ci.org/m-labs/nmigen/builds/565807713?utm_source=github_status&utm_medium=notification

05:21 <_whitenotifier-3> [nmigen] whitequark commented on issue #153: support for memories with N read-only ports + 1 write-only port? - https://git.io/fjS72

05:21 <_whitenotifier-3> [nmigen] whitequark closed issue #153: support for memories with N read-only ports + 1 write-only port? - https://git.io/fj137

05:36 <_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/565807803?utm_source=github_status&utm_medium=notification

05:36 <_whitenotifier-3> [nmigen] Success. 80.74% (+0.01%) compared to 5fd8a79 - https://codecov.io/gh/m-labs/nmigen/commit/995e4adb8c9801c7369e5eaa758545b16705c2a7

05:36 <_whitenotifier-3> [nmigen] Success. 88.88% of diff hit (target 80.73%) - https://codecov.io/gh/m-labs/nmigen/commit/995e4adb8c9801c7369e5eaa758545b16705c2a7

10:24 <zignig> 02:54 <whitequark> zignig: yup sure. feel free to poke me once a week or two if i don't get around to it

10:24 <zignig> https://freenode.irclog.whitequark.org/m-labs/2019-06-27#24852289;

10:26 <whitequark> zignig: actually was looking earlier today. will hopefully look more

11:33 <zignig> whitequark: nice, I'm stuck at macros , I think by making the <Instr> constructor take objects without coding and still have operands means that pseudo instructions and macros just drops out.

11:33 <zignig> that way porting my serial bootloader from v2 , becomes much easier.

11:46 <zignig> oh, and renaming registers.

12:58 <mtrbot-ml> [mattermost] <dpn> whitequark: (How) can I bitcast a TFloat to TInt32 in ARTIQ Python?

23:35 <mtrbot-ml> [mattermost] <kwnminho> kwnminho joined the team.