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<cr1901>
whitequark: In nmigen, what is the purpose of BuildPlan.extract compared to nmigen? Doing a quick grep of nmigen, I can't find it used anywhere (but I know it was used b/c there was a Windows bug tickled in that function)
<cr1901>
crap... I meant BuildProducts.extract
<cr1901>
compared to BuildProducts.get
<whitequark>
it's used in nmigen_boards
<cr1901>
Oh, and I even wrote code that USED it
<cr1901>
go figure
<zignig>
whitequark, cr1901 greetings.
<zignig>
managed to get a big win on my Boneless set up last night. Serial echo.
<cr1901>
Got the logic ported, but... the counter is counting
<zignig>
nice , it that going to be for the PMOD dual 7seg ?
<cr1901>
yes
<cr1901>
the counter is NOT counting8
<cr1901>
*
<whitequark>
zignig: cool!
<zignig>
it was so exciting actually getting a ascii char back...
<zignig>
I have not written much assembly , but having a compare immediate (CMPI) would save a lot of register shuffling.
<zignig>
and the Extened jumps ( flag on the C class ) is not exposed in the ISA.
<whitequark>
zignig: there IS a CMPI instruction
<whitequark>
is it missing somewhere?
<whitequark>
page 15 of the manual mentions it
<whitequark>
zignig: oh, I see the problem
<whitequark>
I never actually pushed the "v3" core
<whitequark>
that has quite a few changes since "v2", which is what you're working with
<whitequark>
I'm going to return to that soon
<zignig>
whitequark: looking forward to it. Luckily the assembler gets is commands straight out of the arch/instr.py
<zignig>
the assembler works at the moment but it still needs lots of TLC , it's not very friendly.
<whitequark>
zignig: yup sure. feel free to poke me once a week or two if i don't get around to it
<whitequark>
i have a lot of the code to do it locally, it's just not in very good shape yet
<whitequark>
and it would be more compact to boot
<zignig>
should be able to fit 16 bonelesses on a tinyBX , boneless tesseract.
* zignig
Mwhahaha
<whitequark>
if I get it down to 350 LUTs then it could be more like 24 of them
<whitequark>
not sure if I could
<zignig>
the uart I ported is pretty fat ( 200 luts ) , i need to do some reading , but I recall you saying that it could be simplified down to shiftregisters and some flags.
<whitequark>
I think an UART can be done in something like 50 LUTs.
<whitequark>
could probably try it now?
<whitequark>
well, it depends on how fast you're clocking it, of course
<zignig>
9600 8n1 , it's the LAW !
<whitequark>
no, I mean, what is your system clock
<whitequark>
since the size of the divider will depend on that
<zignig>
16Mhz default clock on the tinybx.
<whitequark>
if your system clock is 100 MHz and you need 9600, you will spend 28 LUTs just on the divider
<whitequark>
if I'm counting correctly
<zignig>
speaking of which , is nMigen going to have PLL and WARMBOOT primatives ?
<whitequark>
you can use them as instances right now
<zignig>
I've not tried it, but an Instance should work.
<cr1901>
whitequark: Are you supposed to pass the clk down to submodules explicitly?
<zignig>
do you have code for said uart ? or is it speculative at this point ?
<whitequark>
zignig: I'm writing it right now
<whitequark>
hence "I think"
<cr1901>
m = Module()
<cr1901>
m.domains.sync = ClockDomain()
<cr1901>
doesnt seem to be enough
<cr1901>
in the output verilog I get the clock for that module tied to 0
<whitequark>
cr1901: the domain propagation in nmigen works the same as in migen, other than domains are not created implicitly
<whitequark>
in general, you need to create one sync domain at the top, and drive it there
* zignig
is not sure if whitequark is a team of clones or an individual ;)
<whitequark>
this really needs to happen as a part of platform, similar to the default_clk thing... but it's not done yet
<cr1901>
I did, and the children don't receive a working clock
<zignig>
cr1901: m.d.comb += ClockSignal().eq(clk12) needs to be ---.eq(clk12.i)
<zignig>
otherwise you are not getting a wiggling signal.
<whitequark>
zignig: that actually should work
<whitequark>
because a record of one field behaves exactly like that same field
<zignig>
oh ok, good to know.
<cr1901>
not to mention the top module's sync logic is firing
<cr1901>
confirmed on LED breakout
<whitequark>
gimme a sec
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<whitequark>
cr1901: so the problem is that you're not using clock domains correctly.
<whitequark>
two ClockDomain() objects means two clock domains.
<whitequark>
and you are only driving the clock for one of them (in Top, but not in DigitToSegments)
<cr1901>
1. what should the code look like?
<cr1901>
2. DigitsToSegments was developed first. So I put the clock domain object in deliberate to debug it separately and check that the RTLIL looked kosher >>
<cr1901>
I understand normally users don't need to do that, but is the correct solution to always remove the clock domain from submodules once you're done testing them in isolation?
<whitequark>
you can test them without creating a domain explicitly
<cr1901>
Missing If Else Elif, but blinky takes care of that
<zignig>
one of the things that I have been playing with is the 'gizmo' that will automatically bind a device to boneless ext_io
<whitequark>
that's basically misoc
<zignig>
having pmod gizmos would be cool , with the seven segment you just say d = DualSevenSegment(pmod=2) and tada it's attached.
<zignig>
whitequark: indeed, I like rewriting things from scratch so I understand it better...
<whitequark>
zignig: finished the uart. 57 LUT
<zignig>
wow ! , keen to try.
<whitequark>
ok, 59 with frame and overflow error support
<whitequark>
that's pretty close
<cr1901>
I haven't found a use for the pmod ext yet, even for gpio. I should've written down my feelings when they were fresh. Making my own custom pmods that have subsignal names more closely matching the PMODs purpose feels more ergonomic
<zignig>
my long term plan with my Boneless work is to have an interactive console running in the FPGA that can call out the host PC and request new gateware.
<zignig>
save state, upload new image , boot , return to state with new hardware attached.
<zignig>
whitequark: if you are so inclined, can you post/commit the dirty version of the v3 Boneless core, would really like to bash my tiny brain against it.
* zignig
should plan REM sleep in advance, reaches for the rectangle of evil.
<whitequark>
zignig: oh yeah, it looks like the decoder only has ALSR instructions hooked up at all
<zignig>
still , from a quick glance you have made it significantly more compact , the arbiter can squidge it better than the i_<stuff> signal collection.
<whitequark>
yes.
<whitequark>
actually, the cost estimate I have in the spreadsheet is 263 LCs
<whitequark>
but that's a bit too low
<zignig>
+UART and a tethered serial monitor in less that 600 luts for any board in nmigen_boards repo , smells like a stilleto to me.
<zignig>
whitequark: one other thing that struck me a few weeks ago; is making Elaboratable so it can be observed and all the state changes get funneled into a formalzing interface.
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<zignig>
that way debugging state maps becomes a python decorator.
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<whitequark>
zignig: i have absolutely no idea what any of that menas
<whitequark>
*means
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<zignig>
whitequark: ok , just know that I'm enjoying building stuff.
<whitequark>
alright
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<mtrbot-ml_>
[mattermost] <sb10q> got my homebuilt SFPI to work :) unfortunately it seems the piezo broke after a few minutes...
<mtrbot-ml_>
[mattermost] <sb10q> there's voltage on the electrodes, and tapping on the cavity produces bursts of pulses on the photodiode so it looks like there's something damaged in the ceramic
<mtrbot-ml_>
[mattermost] <sb10q> i'm using a piezo ring that is normally used in ultrasonic cleaners
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<Astro->
zynq eth rx/tx works with loopback_local; I wonder if it would emit packets on the zc706 instead of the cora. @sb0: is ethernet plugged in? can I tshark/tcpdump on it?
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