sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<_whitenotifier-3> [nmigen] zignig opened issue #108: Platform Example fails to simulate - https://git.io/fjrOG
<_whitenotifier-3> [nmigen] whitequark commented on issue #108: Platform Example fails to simulate - https://git.io/fjrOC
<_whitenotifier-3> [nmigen] whitequark closed issue #108: Platform Example fails to simulate - https://git.io/fjrOG
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<_whitenotifier-3> [nmigen] zignig commented on issue #108: Platform Example fails to simulate - https://git.io/fjrsl
<_whitenotifier-3> [nmigen] whitequark commented on issue #108: Platform Example fails to simulate - https://git.io/fjrs4
<_whitenotifier-3> [nmigen] programmerjake commented on issue #108: Platform Example fails to simulate - https://git.io/fjrGO
<_whitenotifier-3> [nmigen] whitequark commented on issue #108: Platform Example fails to simulate - https://git.io/fjrGn
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<_whitenotifier-3> [nmigen] zignig commented on issue #108: Platform Example fails to simulate - https://git.io/fjr0H
<_whitenotifier-3> [nmigen] whitequark commented on issue #108: Platform Example fails to simulate - https://git.io/fjrEn
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<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 1 commit to master [+1/-0/±0] https://git.io/fjrEi
<_whitenotifier-3> [m-labs/nmigen] whitequark 0a145ed - vendor.lattice_ecp5: implement.
<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/fjrED
<_whitenotifier-3> [m-labs/nmigen] whitequark f60ceb3 - vendor.xilinx_{spartan6,7series}: speedgrade→speed.
<_whitenotifier-3> [m-labs/nmigen-boards] whitequark pushed 1 commit to master [+2/-0/±0] https://git.io/fjrES
<_whitenotifier-3> [m-labs/nmigen-boards] whitequark 18a80fa - Add Versa ECP5/ECP5-5G support.
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<sb0> whitequark: what's the purpose of get_ixor/get_oxor?
<_whitenotifier-3> [nmigen] whitequark opened issue #109: ECP5 I/O issues - https://git.io/fjrEH
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/550364073?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] Success. 80.71% remains the same compared to 56fe329 - https://codecov.io/gh/m-labs/nmigen/commit/0a145ed2d92dc4911f95b84550630200a64fe5f5
<_whitenotifier-3> [nmigen] Success. Coverage not affected when comparing 56fe329...0a145ed - https://codecov.io/gh/m-labs/nmigen/commit/0a145ed2d92dc4911f95b84550630200a64fe5f5
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/550365663?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] Success. 80.71% remains the same compared to 0a145ed - https://codecov.io/gh/m-labs/nmigen/commit/f60ceb349b1cb7439f85115d6fd255e56f30cd60
<_whitenotifier-3> [nmigen] Success. Coverage not affected when comparing 0a145ed...f60ceb3 - https://codecov.io/gh/m-labs/nmigen/commit/f60ceb349b1cb7439f85115d6fd255e56f30cd60
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<_whitenotifier-3> [nmigen] whitequark commented on issue #109: ECP5 I/O issues - https://git.io/fjrue
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<whitequark> sb0: PinsN
<sb0> whitequark: why not use generic code and the synthesizer?
<sb0> instead of platform-dependent code with LUT instantiations
<whitequark> sb0: so that they don't get optimized into nothing
<whitequark> if you're using pseudo-differential I/O that isn't registered in the IOB you want same delay on both
<sb0> hmm
<whitequark> it's niche, yes
<whitequark> but I just wanted to make it work well no matter the requested settings
<whitequark> I tested it on ice40 and the inverter delay skews the edges quite noticeably
<_whitenotifier-3> [nmigen] whitequark commented on issue #78: Implement XDR buffer factories for all platforms - https://git.io/fjruM
<_whitenotifier-3> [nmigen] whitequark closed issue #78: Implement XDR buffer factories for all platforms - https://git.io/fjEMr
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<whitequark> sb0: should we reword the "under development" README warning in nMigen yet?
<whitequark> I don't really anticipate any more core language changes
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<_whitenotifier-3> [nmigen] whitequark commented on issue #92: Using Yosys with Xilinx Series 7 devices (and non-standard tool flows) - https://git.io/fjrzz
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