sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<sb0> whitequark: so, rust-lld doesn't compile (it breaks due to an incompatibility with some msp430 definitions in llvm), lld-7 doesn't support riscv, and lld-8 isn't compatible with the llvm-7 that rustc requires. i ended up using good old binutils...
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<mtrbot-ml_> [mattermost] <sb10q> @astro why exactly do we need the mozilla overlay for building the stm32 firmware? except for the above linker issue, the embedded rust stuff seems to be working just fine (for riscv) with just this trivial overlay https://git.m-labs.hk/M-Labs/HeavyX/src/branch/master/overlay.nix
<mtrbot-ml_> [mattermost] <sb10q> and the original nixpkgs rust/cargo/etc. packages
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<whitequark> sb: are you building rustc against rust's llvm fork?
<whitequark> cr1901: yes, connector pins are (in general, by convention) using the same numbering as the physical schematics
<whitequark> i believe this is absolutely necessary for larger and less common connectors
<mtrbot-ml_> [mattermost] <sb10q> whitequark: no, should I?
<whitequark> sb: in general, yes
<whitequark> it has some patches on top of upstream llvm, which you are hitting
<whitequark> or rather their absence
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<plaes> rjo: any idea how to handle the openocd repo fork?
<mtrbot-ml_> [mattermost] <sb10q> plaes: handle how?
<plaes> I rebased it on-top of upstream master and apparently only two extra commits are required: https://github.com/plaes/openocd/commits/m-labs-master
<plaes> what worries me is that alphamax (netv2) is already pushing stuff on top of m-labs fork
<mtrbot-ml_> [mattermost] <sb10q> do you want to try and get it merged?
<plaes> thruth is that I don't know how to actually handle it
<mtrbot-ml_> [mattermost] <sb10q> well, that's more of a question for upstream openocd :)
<rjo> plaes: whitesuqark should push his commit upstream and i should push mine. that's it. what alphamax does is his choice. they way openocd reviews patches it doesn't matter much what branch they are based on (apart from functional dependencies).
<plaes> ok, cool..
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<rjo> plaes: i'll try pushing both patches upstream now
<plaes> \o/
<rjo> and if you are reasonably confident you did a proper job rebasing then i'll also gladly push that to m-labs/openocd
<rjo> thanks for the analysis and the rebase!
<plaes> yeah.. there were 2 or 3 patches that required some "manual" fixing but these had been already fixed upstream
<rjo> what's with the format-overflow and implicit-fallthrough patches?
<plaes> these had been fixed upstream
<plaes> fallthrough commit: 9364b0dba45
<plaes> overflow commit: 079d78f7de91
<rjo> plaes: ok. thanks
<rjo> and reconciled the github branch keeping both histories (we'll probably need that for our packages)
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<whitequark> sb: rjo: why is the kc705 migen platform (among others) never using DiffPairs ?
<whitequark> all differential signals are defined with explicit _p and _n suffixes
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<_whitenotifier-3> [nmigen] jfng opened pull request #89: vendor.xilinx_s7: implement. - https://git.io/fjzfb
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/542227519?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] codecov[bot] commented on pull request #89: vendor.xilinx_s7: implement. - https://git.io/fjzJq
<_whitenotifier-3> [nmigen] Success. 80.6% remains the same compared to b45c511 - https://codecov.io/gh/m-labs/nmigen/compare/b45c5119f573e156a3aad4a362ca210d6e40505e...a96ae33707022eb9a5c128d4acb3e64c9ea6409f
<_whitenotifier-3> [nmigen] Success. Coverage not affected when comparing b45c511...a96ae33 - https://codecov.io/gh/m-labs/nmigen/compare/b45c5119f573e156a3aad4a362ca210d6e40505e...a96ae33707022eb9a5c128d4acb3e64c9ea6409f
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<mtrbot-ml_> [mattermost] <sb10q> Probably because DiffPairs was introduced after those platforms, and nobody refactored
<_whitenotifier-3> [nmigen] whitequark reviewed pull request #89 commit - https://git.io/fjzJC
<_whitenotifier-3> [nmigen] whitequark reviewed pull request #89 commit - https://git.io/fjzJW
<_whitenotifier-3> [nmigen] whitequark reviewed pull request #89 commit - https://git.io/fjzJl
<_whitenotifier-3> [nmigen] whitequark reviewed pull request #89 commit - https://git.io/fjzJ8
<whitequark> hm, so i'm looking at RGMII
<whitequark> and i think the nmigen XDR primitives are sufficient to implement portable RGMII
<whitequark> the TX half is obviously okay, and the RX half is okay if the clock delay in PHY is appropriately configured
<whitequark> or, if an appropriate constraint is added in the platform file
<cr1901> whitequark: > i believe this is absolutely necessary for larger and less common connectors
<cr1901> Yup, this makes sense now that I understand it. And it's the right convention IMO. Just threw me off b/c it is different from omigen
<cr1901> Could you possibly review the icebreaker PR this morning?
<whitequark> cr1901: oh oops, i wasn't watching that repo somehow
<_whitenotifier-3> [nmigen-boards] whitequark synchronize pull request #2: Add icebreaker platform. - https://git.io/fjubz
<_whitenotifier-3> [m-labs/nmigen-boards] whitequark pushed 1 commit to master [+1/-0/±0] https://git.io/fjzUz
<_whitenotifier-3> [m-labs/nmigen-boards] cr1901 d21c2e2 - Add icebreaker platform.
<_whitenotifier-3> [nmigen-boards] whitequark closed pull request #2: Add icebreaker platform. - https://git.io/fjubz
<cr1901> tyvm
<_whitenotifier-3> [nmigen] jfng synchronize pull request #89: vendor.xilinx_s7: implement. - https://git.io/fjzfb
<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 1 commit to master [+1/-0/±0] https://git.io/fjzTa
<_whitenotifier-3> [m-labs/nmigen] jfng f26e612 - vendor.xilinx_7series: implement.
<_whitenotifier-3> [nmigen] whitequark closed pull request #89: vendor.xilinx_s7: implement. - https://git.io/fjzfb
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/542265837?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] Success. 80.6% remains the same compared to b45c511 - https://codecov.io/gh/m-labs/nmigen/compare/b45c5119f573e156a3aad4a362ca210d6e40505e...71f95c407e05bf8fdb505a53fd9e002ba2095710
<_whitenotifier-3> [nmigen] Success. Coverage not affected when comparing b45c511...71f95c4 - https://codecov.io/gh/m-labs/nmigen/compare/b45c5119f573e156a3aad4a362ca210d6e40505e...71f95c407e05bf8fdb505a53fd9e002ba2095710
<cr1901> whitequark: Do you think the platform files are more or less stabilized at this point?
<whitequark> cr1901: to some extent
<cr1901> I don't want to write a how-to-port blog post while the files are still in flux (nor do I want to add more platforms until then- I ported icebreaker b/c that's what I have on hand right now ;)...)
<whitequark> cr1901: the only change i can foresee right now is adding back default_clk
<whitequark> but probably nothing beyond that
<cr1901> Ack. nextpnr issues notwitstanding, there may also be a reason to bring back default clock (or allow platforms to extend it) for FPGAs w/ internal oscillators (Mach series).
<cr1901> For tinyfpga A/Mach, I dded a "default_osch_period" class var that normally shadows "default_clk_period" unless you're also using a external clock; both need to be set to the same value if using the internal oscillator.
<cr1901> I could probably handle this edge case nicer in nmigen
<whitequark> i think if i reintroduce the automatic generation of a CRG (this isn't quite possible yet, it needs to hook into Fragment.prepare), then it should just call a platform method
<cr1901> provide a default implemenation (or a mixin) that platforms can call (inherit) from, since the default CRG works in the vast majority of cases?
<_whitenotifier-3> [nmigen-boards] zignig opened pull request #3: pwm breathing with phase offset - https://git.io/fjzkI
<whitequark> cr1901: yes
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<_whitenotifier-3> [nmigen-boards] whitequark commented on pull request #3: pwm breathing with phase offset - https://git.io/fjzks
<_whitenotifier-3> [nmigen-boards] zignig commented on pull request #3: pwm breathing with phase offset - https://git.io/fjzkl
<_whitenotifier-3> [nmigen-boards] zignig closed pull request #3: pwm breathing with phase offset - https://git.io/fjzkI
<zignig> it should look cool on the ice breaker.
<cr1901> zignig: It does look nice :P
* zignig activates the blinkinator.
<zignig> :)
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<whitequark> cr1901: hmm
<whitequark> are you sure you didn't swap DQ0 and DQ1?
<cr1901> I swapped the order they were listed in the nmigen file, but I remembered to swap the pins too
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<cr1901> I swapped them for consistency w/ the order they are presented in tinyfpga bx
<whitequark> nvm, it matches schematic
<whitequark> I think we should just abstract that
<whitequark> have a function that returns 1x, 2x and 4x (if available) resources
<whitequark> *way* too error prone to do it by hand each time
<cr1901> Would this function also work for say, PMOD spiflash boards? Presumably the reason you can abstract it is because each family hardcodes the pins you use for a single SPI flash
<cr1901> (but not others)
<whitequark> I mean, all SPI flashes (that I know of) have the same pinout in the sense that MOSI is always DQ[0]
<whitequark> so you could do something like SPIFlashResources(0, cs_n="F7", mosi="G6") and so on
<cr1901> ... yea sounds like that'll work. I didn't personally verify 4x spiflash works on icebreaker on nmigen. However, I know from my own testing that it works on omigen, so as long as I copied the pinout properly, there shouldn't be any problems.
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<whitequark> and actually they should be called wp_n and hold_n
<whitequark> not wp and hold
<cr1901> now's the right time to change that before backwards compat ruins everything
<whitequark> yeah, there's a lot of these issues...
<whitequark> they also probably should be reset to 1
<whitequark> which is gonna be *real* annoying to implement
<whitequark> or i guess they could be just tristated by default?
<cr1901> I think that's beyond the scope of what platforms should provide. tristate by default seems reasonable if wp/hold_n are known to be pulled up
<cr1901> wp_n*
<whitequark> well the thing is
<whitequark> if you currently request an spiflash
* cr1901 checks misoc and finds the spiflash core doesn't touch wp and hold at all
<mtrbot-ml_> [mattermost] <astro> we need the mozilla-overlay for non-stable rustc. I'll have a look at this alternative.
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<whitequark> cr1901: ok, yeah, so what i was saying is
<whitequark> if you request wp in nmigen, it will be added as an output
<whitequark> and the default for an output is to output a 0
<whitequark> which will make it write-protected and unresponsive
<cr1901> Ahhhh
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<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fjzs1
<_whitenotifier-3> [m-labs/nmigen] whitequark 12e8fe4 - build.dsl: fix precondition check in Pins.
<_whitenotifier-3> [m-labs/nmigen-boards] whitequark pushed 1 commit to master [+2/-0/±4] https://git.io/fjzsM
<_whitenotifier-3> [m-labs/nmigen-boards] whitequark bb52dfb - Factor out SPI flash resource definition.
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/542464952?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] Success. 80.6% (+0%) compared to f26e612 - https://codecov.io/gh/m-labs/nmigen/commit/12e8fe484d204f637e5ee38286346a84dec83b1f
<_whitenotifier-3> [nmigen] Success. 100% of diff hit (target 80.6%) - https://codecov.io/gh/m-labs/nmigen/commit/12e8fe484d204f637e5ee38286346a84dec83b1f
<mtrbot-ml_> [mattermost] <astro> I cannot get the compiler-builtins to build with rustc 1.32.0 from nixos 19.03. could we switch stm32 to nixos unstable? then I'd give it another try.
<mtrbot-ml_> [mattermost] <astro> oh, you can get rust nightly without the mozilla overlay?
<mtrbot-ml_> [mattermost] <astro> ah, heavyx uses nixos unstable indeed... *rebuilding*
<_whitenotifier-3> [nmigen] jfng opened pull request #90: vendor.xilinx_7series: fix typos. - https://git.io/fjzZI
<_whitenotifier-3> [nmigen] jfng opened pull request #91: vendor.xilinx_spartan6: implement. - https://git.io/fjzZL
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/542506933?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] codecov[bot] commented on pull request #91: vendor.xilinx_spartan6: implement. - https://git.io/fjzZY
<_whitenotifier-3> [nmigen] Success. Coverage not affected when comparing 12e8fe4...f53c8c4 - https://codecov.io/gh/m-labs/nmigen/compare/12e8fe484d204f637e5ee38286346a84dec83b1f...f53c8c45d41f3b2458338a0d1442264b91b27c74
<_whitenotifier-3> [nmigen] Success. 80.6% remains the same compared to 12e8fe4 - https://codecov.io/gh/m-labs/nmigen/compare/12e8fe484d204f637e5ee38286346a84dec83b1f...f53c8c45d41f3b2458338a0d1442264b91b27c74
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/542506732?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] mithro opened issue #92: Using Yosys with Xilinx Series 7 devices (and non-standard tool flows) - https://git.io/fjzZ0
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