#m-labs on 2019-12-24 — irc logs at freenode.irclog.whitequark.org

2019-04-01 16:30 sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs

00:02 <Astro-_> I still have not yet found what's wrong with my spi flash instruction on the zc706. :(

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01:23 <mtrbot-ml> [mattermost] <sb10q> @astro with openocd? rust? both?

01:24 <mtrbot-ml> [mattermost] <sb10q> @astro have you looked into migen-axi at all?

01:27 <mtrbot-ml> [mattermost] <sb10q> @astro that's one of some intermittent test failures that relate to the performance of the core device. if you restart the build it may work. annoying and we have little bandwidth to fix them...

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01:41 <_whitenotifier-5> [nmigen-stdio] sbourdeauducq reviewed pull request #2 commit - https://git.io/JeF6H

01:42 <_whitenotifier-5> [nmigen-stdio] sbourdeauducq reviewed pull request #2 commit - https://git.io/JeF67

01:44 <_whitenotifier-5> [nmigen-stdio] sbourdeauducq reviewed pull request #2 commit - https://git.io/JeF6A

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01:51 <_whitenotifier-5> [nmigen-stdio] sbourdeauducq reviewed pull request #2 commit - https://git.io/JeF6j

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01:52 <_whitenotifier-5> [nmigen-stdio] sbourdeauducq reviewed pull request #2 commit - https://git.io/JeFiU

01:53 <_whitenotifier-5> [nmigen-stdio] sbourdeauducq reviewed pull request #2 commit - https://git.io/JeFiT

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02:01 <_whitenotifier-5> [nmigen-boards] sbourdeauducq commented on pull request #38: Option to factor out "clk" from "spi_flash" on Lattice ECP5 - https://git.io/JeFiL

02:05 <_whitenotifier-5> [nmigen-boards] sbourdeauducq commented on pull request #38: Option to factor out "clk" from "spi_flash" on Lattice ECP5 - https://git.io/JeFis

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03:37 <_whitenotifier-5> [nmigen] whitequark commented on issue #254: Find solution to translate values to strings for Symbiyosys vcd files - https://git.io/JeFP6

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10:11 <Sarayan> whitequark, are you perchance around?

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10:55 <whitequark> Sarayan: sure

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12:59 <Sarayan> whitequark: I could use some recommendations on converting a nmos schematic (via6522) to nmigen

13:00 <Sarayan> it's nmos, so it doesn't know about edges, obviously

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13:00 <Sarayan> it has a single clock as input, and uses three clock signals

13:00 <Sarayan> - the clock itself, for I guess signals that will be available on the next negative pulse

13:01 <Sarayan> - a pulse generated on a negative edge, for I guess read things on the negative edge

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13:02 <Sarayan> - and an inverted clock with delayed start which happens just after the pulse is ended, for I guess signals that should be then read on the next positive edge

13:03 <Sarayan> I'm not 100% sure what all that should look like in nmigen land, to have something sane

13:04 <Sarayan> I would guess, if I have something, in particular a latch, set on phi2 or the pulse, do it on ck0p, and on the inverted do it on ck0n?

13:06 <Sarayan> https://og.kervella.org/via6522/via6522/ fwiw

13:07 <Sarayan> single clock, so easier than pretty much anything else :-)

13:07 <Sarayan> and in particular the wd :-)

13:07 <Sarayan> plus it's small

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16:23 <whitequark> hmm

16:23 <whitequark> i'm not entirely sure tbh, but it sounds about right to me

16:45 <Sarayan> ok, I'll try and we'll see

16:45 <Sarayan> hacking a simpler but better sim in my schematics viewer to make it easier to extract the combinatronics

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17:51 <Sarayan> here we go, it's simming

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21:45 <Astro-_> @sb10q still trying to program the flash in rust. once that's working, openocd nand driver should be akin to modifying existing drivers.

21:46 <Astro-_> I haven't given up but I'm aware it is taking way too long :(

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