sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<zignig> has anyone tried the csr in nmigen-soc ?
<zignig> I'm getting a weird fence post error where the data is one cycle old on a bound serial port.
<zignig> using the bonless cpu , I'm combinatorial binding the mem interface to the bus and then sync binding to the elaboratable.
<zignig> not sure why it's delayed by one.
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<mtrbot-ml> [mattermost] <sb10q> @harryho ^
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<_whitenotifier-5> [nmigen] Fatsie commented on issue #285: Making Instance with clock compatible with EnableInserter - https://git.io/Jeb2n
<_whitenotifier-5> [nmigen] whitequark commented on issue #285: Making Instance with clock compatible with EnableInserter - https://git.io/Jeb2K
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<_whitenotifier-5> [nmigen] Fatsie commented on issue #285: Making Instance with clock compatible with EnableInserter - https://git.io/JebaV
<_whitenotifier-5> [nmigen] whitequark commented on issue #285: Making Instance with clock compatible with EnableInserter - https://git.io/Jeba6
<Sarayan> whitequark, around?
<whitequark> Sarayan: yes
<Sarayan> I have a register that is written to when ck0n if the chip is selected and the address is correct
<Sarayan> recommendations on writing that?
<whitequark> with m.If(cs & (addr == 0b000)): m.d.ck0n += reg.eq(din)
<whitequark> something along these lines
<Sarayan> nice
<Sarayan> that's what I planned to do given the tutorial, excellent
<Sarayan> also, what's the recoomended way to sim to testat that point?
<whitequark> pysim should work just fine
<whitequark> IIRC I wrote a simulation driver for you earlier? if it's not in logs I can do it again
<Sarayan> yeah, you did, and it works well
<Sarayan> I was wondering if the recommended way had changed with your recent work
<whitequark> nope, works the same
<whitequark> the interface didn't change actually
<Sarayan> ok, nice
<Sarayan> you'll have to teach me cxxsim at one point, but for the 6522 pysim is good enough by far
<Sarayan> thanks :-)
<Sarayan> oh, do you know of a nmigen 6502 (the cpu) or will I have to do it myself?
<whitequark> nope
<Sarayan> okay
<Sarayan> will be an interesting exercise
<Sarayan> at least it's single clock too
<whitequark> good luck!
<Sarayan> :-)
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<_whitenotifier-5> [nmigen] Fatsie commented on issue #285: Making Instance with clock compatible with EnableInserter - https://git.io/Jebwa
<_whitenotifier-5> [nmigen] whitequark commented on issue #285: Making Instance with clock compatible with EnableInserter - https://git.io/Jebww
<_whitenotifier-5> [nmigen] Fatsie commented on issue #285: Making Instance with clock compatible with EnableInserter - https://git.io/Jebw6
<_whitenotifier-5> [nmigen] whitequark commented on issue #285: Making Instance with clock compatible with EnableInserter - https://git.io/Jebwx
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<Sarayan> wtf?
<Sarayan> TypeError: Attempted to convert nMigen value to boolean
<Sarayan> m.d.comb += self.m_ora.i_or_r.eq(self.c_r & (self.c_rs_latch_1 == 0xf | self.c_rs_latch_1 == 0x1))
<Sarayan> I guess I may need more parenthesis?
<Sarayan> yeah, looks so
<Sarayan> ah, deprecations insults
<_whitenotifier-5> [nmigen] Fatsie commented on issue #285: Making Instance with clock compatible with EnableInserter - https://git.io/JeboZ
<Sarayan> whitequark help help :-)
<Sarayan> in the via6522, using test.py there, why don't I see anything changing under gtkwave?
<Sarayan> got it
<Sarayan> generator functions ftw
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<Sarayan> hmmm, still not working in practice
<Sarayan> duh, me st00pid
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<Sarayan> mhhh, I must be doing something obviously wrong, and I have no idea what
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<Sarayan> oh damn, you can't have subfunctions
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<_whitenotifier-5> [nmigen] AsuMagic opened issue #286: Misleading error when trying to use self.comb when inheriting from Module - https://git.io/JebP0
<Sarayan> yay it seems to work. For future reference, pysim2 forgets to add the inputs to the list of signals to trace
<Sarayan> that's rather annoying :-)
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<adamgreig> Sarayan: it's an open issue #280
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<Sarayan> adamgreig: Ah ok
<Sarayan> I've just added a quick hack to be able to add random signals from the test code
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