02:44 <cr1901_modern> sb10q: I'm cleaning up my todoist, and I have a number of migen issues I documented there that I never got around to fixing. Even if they are WONTFIXes, do you object if I open issues for them (and maybe fix some of them if I get the time)?

03:05 <mtrbot-ml> [mattermost] <sb10q> you can open issues, why not?

09:03 <_whitenotifier-5> [nmigen] whitequark commented on issue #285: Making Instance with clock compatible with EnableInserter - https://git.io/JebAO

09:51 <mtrbot-ml> [mattermost] <sb10q> @astro any ideas about this bug? https://git.m-labs.hk/M-Labs/zc706/issues/7

09:52 <mtrbot-ml> [mattermost] <sb10q> no idea why that appeared, also tried older versions of openocd/gdb scripts that used to work, the issue persists

11:39 <ZirconiumX> whitequark: if I wanted to donate an SPI interface to nMigen, would that go in nmigen-stdio?

11:41 <whitequark> yes

11:41 <mtrbot-ml> [mattermost] <sb10q> ZirconiumX: basically yes, but it should be a low-level layer only (only expose SPI control signals and without e.g. CSRs which go somewhere else)

11:41 <mtrbot-ml> [mattermost] <sb10q> you may also want to coordinate with @harryho who's been working on SPI flash support also

11:41 <whitequark> keep in mind that I'm still working out conventions for cores in nmigen-stdio so it can take quite a bit of time and changes for it to be merged

11:42 <ZirconiumX> What I have at the moment is essentially a glorified shift register attached to a small FSM to transfer it

11:43 <ZirconiumX> I'm trying to drive an SD card here, so it's not quite the same as SPI flash

12:01 <mtrbot-ml> [mattermost] <rikstarmans> Hey all, I have some questions I am trying to connect the main clock to the instance SB_PLL40_PAD. This requires me to request the main clock which results in the same issue outlined here https://freenode.irclog.whitequark.org/m-labs/2019-09-08.. "ResourceError: Resource clk12#0 has already been requested "

12:02 <whitequark> does your design have multiple clock domains, or do you just want to use PLL to have a single domain with a higher frequency?

12:02 <mtrbot-ml> [mattermost] <rikstarmans> How do I circumvent this problem? It was pointed out that I should give my clock domain the 'sync` name: `cd_pll = ClockDomain(jsync') . This doesn't work at all..

12:04 <mtrbot-ml> [mattermost] <rikstarmans> in the end it only uses one clock domain... the result from SB_PLL40_PAD

12:04 <whitequark> can you post your code?

12:04 <mtrbot-ml> [mattermost] <rikstarmans> I am trying to rebuild this example in migen https://github.com/cliffordwolf/icotools/blob/master/examples/icezero/icezero.v ...

12:04 <mtrbot-ml> [mattermost] <rikstarmans> okay will post my code

12:04 <whitequark> wait, migen or nmigen?

12:07 <_whitenotifier-5> [nmigen] ZirconiumX opened issue #287: Document simulator commands - https://git.io/Jebhk

12:07 <mtrbot-ml> [mattermost] <rikstarmans> migen... this is what i have so far https://github.com/hstarmans/migen_tests/blob/master/migen/spi_memmapping/spi_memmapping.py

12:08 <mtrbot-ml> [mattermost] <rikstarmans> there are several issues... one is that I can't define the clock domain used by my finite state machine

12:09 <_whitenotifier-5> [nmigen] whitequark commented on issue #287: Document simulator commands - https://git.io/JebhI

12:09 <_whitenotifier-5> [nmigen] whitequark closed issue #287: Document simulator commands - https://git.io/Jebhk

12:10 <whitequark> ah sorry, ask someone else for migen

12:11 <mtrbot-ml> [mattermost] <rikstarmans> should I already use nmigen?

12:14 <whitequark> you could if you want, but all I'm saying is I don't remember all the intricacies of migen and so can't help you