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<zignig>
whitequark: I am a victim of my own automation , old code still works fine.
<zignig>
whitequark: so my question becomes , how would you go about attaching a CSR mplex to the Boneless external interface.
<zignig>
the once cycle delay in fetching the shadow register value seems to make the boneless get the value _next_ read.
<zignig>
currently I have bus->[comb]->CSR and then [sync]-> to the Elaboratable.
<whitequark>
I'm going to look at it closely after I clear the current backlog of issues
<whitequark>
it'll take a bit of time though
<zignig>
whitequark: no problem, I thought I was going crazy debugging this issue , GKTwave and a big screen to the rescue. ;)
<zignig>
when you have some boneless time , it would be cool if we can merge tpwrules new instruction set too. :)
<whitequark>
yeah
<tpw_rules>
:3
<zignig>
tpw_rules: o/
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<_whitenotifier-3>
[nmigen] whitequark commented on issue #304: ResetSynchronizer clockdomain in submodule is not renamed properly with multiple submodule instances - https://git.io/JvkLg
<_whitenotifier-3>
[nmigen] whitequark reopened issue #304: ResetSynchronizer clockdomain in submodule is not renamed properly with multiple submodule instances - https://git.io/JvJWe
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<_whitenotifier-3>
[m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/Jvkmy
<_whitenotifier-3>
[nmigen] whitequark closed issue #304: ResetSynchronizer clockdomain in submodule is not renamed properly with multiple submodule instances - https://git.io/JvJWe
<_whitenotifier-3>
[nmigen] whitequark commented on issue #304: ResetSynchronizer clockdomain in submodule is not renamed properly with multiple submodule instances - https://git.io/JvkY5
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<_whitenotifier-3>
[nmigen-boards] nicolas-robin opened pull request #46: artyz7: fix attribute name - https://git.io/JvkBB
<_whitenotifier-3>
[nmigen] nicolas-robin opened issue #307: AssertionError domain.name not in self.domains - https://git.io/JvkBo
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<MikeP>
Hi folks, I've been really enjoying learning nmigen, and came here in hopes of answering a question I couldn't figure out from the source.
<ZirconiumX>
"don't ask to ask, just ask" is a motto of mine
<MikeP>
I'm trying to get something to happen on the negative edge of the default clock domain
<MikeP>
First dumb thing I tried was: m.domains.neg = ClockDomain("sync", clk_edge="neg", local=True)
<MikeP>
but (in simulation at least) the "neg" signal stays at 0
<MikeP>
Is there a way to do this?
<ZirconiumX>
MikeP: Judging by the docs, your code is overwriting the `sync` domain
<ZirconiumX>
Because the "sync" there is not the source clock but the clock name
<MikeP>
fwiw I also tried ClockDomain("clk", clk_edge="neg", local=True)