sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<zignig> whitequark: I am a victim of my own automation , old code still works fine.
<zignig> whitequark: so my question becomes , how would you go about attaching a CSR mplex to the Boneless external interface.
<zignig> the once cycle delay in fetching the shadow register value seems to make the boneless get the value _next_ read.
<zignig> currently I have bus->[comb]->CSR and then [sync]-> to the Elaboratable.
<whitequark> I'm going to look at it closely after I clear the current backlog of issues
<whitequark> it'll take a bit of time though
<zignig> whitequark: no problem, I thought I was going crazy debugging this issue , GKTwave and a big screen to the rescue. ;)
<zignig> when you have some boneless time , it would be cool if we can merge tpwrules new instruction set too. :)
<whitequark> yeah
<tpw_rules> :3
<zignig> tpw_rules: o/
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<_whitenotifier-3> [nmigen] whitequark commented on issue #304: ResetSynchronizer clockdomain in submodule is not renamed properly with multiple submodule instances - https://git.io/JvkLg
<_whitenotifier-3> [nmigen] whitequark reopened issue #304: ResetSynchronizer clockdomain in submodule is not renamed properly with multiple submodule instances - https://git.io/JvJWe
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<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/Jvkmy
<_whitenotifier-3> [m-labs/nmigen] whitequark a7be3b4 - hdl.ir: resolve hierarchy conflicts before creating missing domains.
<_whitenotifier-3> [nmigen] whitequark closed issue #304: ResetSynchronizer clockdomain in submodule is not renamed properly with multiple submodule instances - https://git.io/JvJWe
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/638786320?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] Success. 82.19% (+0.01%) compared to 7cb3095 - https://codecov.io/gh/m-labs/nmigen/commit/a7be3b480adbf18006b34f8aae1b73e17d092e26
<_whitenotifier-3> [nmigen] Success. 100% of diff hit (target 82.17%) - https://codecov.io/gh/m-labs/nmigen/commit/a7be3b480adbf18006b34f8aae1b73e17d092e26
<_whitenotifier-3> [nmigen] Success. Absolute coverage decreased by -0.07% but relative coverage increased by +17.82% compared to 7cb3095 - https://codecov.io/gh/m-labs/nmigen/commit/a7be3b480adbf18006b34f8aae1b73e17d092e26
<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/638786320?utm_source=github_status&utm_medium=notification
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<_whitenotifier-3> [nmigen] whitequark commented on issue #304: ResetSynchronizer clockdomain in submodule is not renamed properly with multiple submodule instances - https://git.io/JvkY5
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<_whitenotifier-3> [nmigen-boards] nicolas-robin opened pull request #46: artyz7: fix attribute name - https://git.io/JvkBB
<_whitenotifier-3> [nmigen] nicolas-robin opened issue #307: AssertionError domain.name not in self.domains - https://git.io/JvkBo
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<MikeP> Hi folks, I've been really enjoying learning nmigen, and came here in hopes of answering a question I couldn't figure out from the source.
<ZirconiumX> "don't ask to ask, just ask" is a motto of mine
<MikeP> I'm trying to get something to happen on the negative edge of the default clock domain
<MikeP> First dumb thing I tried was: m.domains.neg = ClockDomain("sync", clk_edge="neg", local=True)
<MikeP> but (in simulation at least) the "neg" signal stays at 0
<MikeP> Is there a way to do this?
<ZirconiumX> MikeP: Judging by the docs, your code is overwriting the `sync` domain
<ZirconiumX> Because the "sync" there is not the source clock but the clock name
<MikeP> fwiw I also tried ClockDomain("clk", clk_edge="neg", local=True)
<ZirconiumX> Hmm
<ZirconiumX> ClockDomain(m.d.sync, clk_edge="neg", local=True) maybe?
<ZirconiumX> It's asking for a Signal, not a string
<ZirconiumX> ...I'm getting it mixed up with the clk attribute
<ZirconiumX> Actually, what if we just leave it at the default and let nMigen figure it out
<ZirconiumX> MikeP: So, I think you're overwriting the sync domain with an undriven clock domain, which is why nothing happens
<MikeP> btw which docs are you looking at?
<ZirconiumX> The source itself
<MikeP> (and thanks for looking at this)
<MikeP> ah gotcha
<ZirconiumX> I think you'd need to supply a clock to `clk`, but I don't know how to do that at present.
<MikeP> I originally got the idea for how this might work from Robert Baruch's tutorial here: https://github.com/RobertBaruch/nmigen-tutorial/blob/master/3_modules.md
<MikeP> The section "Tip: clock domains with the same clock but different edges"
<ZirconiumX> Possibly something for whitequark when she's around
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<_whitenotifier-3> [nmigen-boards] whitequark closed pull request #46: artyz7: fix attribute name - https://git.io/JvkBB
<_whitenotifier-3> [m-labs/nmigen-boards] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JvkEE
<_whitenotifier-3> [m-labs/nmigen-boards] nicolas-robin fae1ad4 - artyz7: fix attribute name.
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