sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<mtrbot-ml> [mattermost] <sb10q> MikeP: there are annoying issues with Rust on 19.09
<mtrbot-ml> [mattermost] <sb10q> MikeP: you can get a copy of nixpkgs 19.03 and then backport the new nextpnr into that. that should be quite easy afaik, perhaps even just dropping in the newer nextpnr .nix files, replacing the old ones
<mtrbot-ml> [mattermost] <sb10q> but if you don't need Rust then 19.09 has no big issues that I know of
<_whitenotifier-3> [nmigen-soc] HarryHo90sHK synchronize pull request #6: wishbone: A proposal to add Interconnect & related SoC building blocks - https://git.io/JvYDM
<_whitenotifier-3> [nmigen-soc] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen-soc/builds/643684388?utm_source=github_status&utm_medium=notification
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<_whitenotifier-3> [nmigen-stdio] HarryHo90sHK opened pull request #5: eth: A proposal to add Ethernet interface & RGMII transceiver module - https://git.io/JvOBZ
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<Sarayan> If I want to do a semi-complex design in nmigen and have it run real-time for a 8MHz clock or so in simulation (say the video pipeline of a konami arcade game), how can I go about it?
<Sarayan> should I go through yosis/cxx-generation, should I add C++ generation to nmigen, even better ideas?
<Sarayan> Pretty much, I want to constraints of hardware to be sure it works, but I don't expect to run it on a fpga in the near term
<whitequark> yosys' write_cxxsim should be helpful here
<whitequark> but... 8 MHz might be optimistic
<whitequark> I'm not saying it *won't* work, but it's pretty high
<Sarayan> well, that's the pixel clock
<Sarayan> I won't die if it's not realtime, it would just be nice
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