<kmj>
Anyone happen to know about using the HPDMC in a SDRAM (non-ddr) environment on a smaller fpga like Cyclone III or Spartan-3e?
<lekernel>
kmj: yeah, it's used with sdr on cyclone2 in the zet86 project
<aeris>
adamw_ *\o/*
<adamw_>
aeris, hi
<CIA-45>
flickernoise: Sebastien Bourdeauducq master * re7d1b14 / patches/Lekernel - Eerie Beri.fnp : New patch (for video in) - http://bit.ly/gaiY68
<kmj>
lekernel: I've downloaded zet with the modified hpdmc. I've got it to synthesize, but I still have to figure out to drive the darn thing.
<lekernel>
who wants to go to London?
<kristianpaul>
seems not you ;-)
<kristianpaul>
oh, i see (mail)
<lekernel>
i'm going next week... bad schedule :(
<kristianpaul>
Fallenou: telnet (milkymist_networking), dint worked for me, and i dint tried on qemu as i have a M1 bord with me
<kristianpaul>
Fallenou: anyway, i'll it again and document my results including a pcap capture
<kristianpaul>
i'll do it*
<kmj>
anyone else want to pull their hair out dealing with dram memory controllers?
<kmj>
or is it just me? :)
<lekernel>
from what i've heard, it's a recurrent problem in most fpga hobbyist and even industrial projects :)
<lekernel>
i've had my share of issues with it as well...
<lekernel>
but it's also a very instructive thing to do. actually, it makes it easier to judge the technical quality of projects by looking at whether they got the DRAM to work or not...
<lekernel>
since opencores contains hundreds of pieces of worthless crap, you need fast criteria like this :)
<kmj>
lekernel: hahaha
<kmj>
lk: it is a recurrent problem.  I first tried with Xilinx, using their Memory Interface Generator(MIG) where they auto-generate a memory controller.
<kmj>
Their controller is approximately 7300 lines of code.
<kmj>
While I think the idea of "opencores" is a great one --- in all practicality, most don't work ----or likely don't work on the hardware you have.
<kmj>
The auto-generating memory controller is a pretty awesome concept. They claim to have verified every possible output.
<kmj>
Even USING pre-made controllers is hard.
<kmj>
After screwing around for a couple hours, I (think) I've managed to get zet's version of the hpdmc to initialize some memory, I think.
<lekernel>
use a simulator...
<kmj>
but of course since I haven't written a read/write state machine(s) yet, I can't know. There's no real "INIT_DONE" signal sent back from the memory
<lekernel>
yup. that's what the "hard" in "hardware" stands for.
<kmj>
lek: That's a possibility.  Assuming that I have an HDL implementation for a DRAM chip that is reliable.
<lekernel>
micron provides good verilog models for their chips
<kmj>
zet included a memory chip, but I haven't checked the data sheet to see if its the same
<kmj>
lek: that's pretty neat that they do that. I guess I'm surprised. I would think it would have to be pretty reliable
<lekernel>
SDRAMs are all very similar... there are JEDEC standards for them
<kmj>
Isn't the JEDEC just physical and maybe protection from ESD, etc?
<lekernel>
if you use hpdmc and get the timings, the geometry and the initialization sequence right, it should work with your other chip
<kmj>
Assuming the width, number of banks, performance etc is the same
<kmj>
but that's big assumptions
<lekernel>
you probably have to change that
<kmj>
That seems like a big change to me. but I'm new to this.
<kmj>
I've got some working FPGA projects
<kmj>
so I know enough to hurt myself
<lekernel>
actually don't even try without checking first, because there's a high probability they aren't the same, and it won't work if there's a problem there
<kmj>
right
<lekernel>
or worse, you'll get aliased memory addresses and other niceties
<lekernel>
which can give you a lot of debugging pain when your system doesn't work because the data in DRAM is corrupted
<kmj>
Sure.
<kmj>
In comparison to on-chip resources like m9k from altera or block rams from xilinx, DRAM is ridicuously more complicated.
<kmj>
SRAM is nice but expensive and not enough to go around
<kmj>
I used some serial memory, and that is nice, but same issues as SRAM
<kmj>
I was checking out tmplab earlier
<lekernel>
yeah, DRAM is difficult, but there's no way around, so bite the bullet :)
<kmj>
haha. I've tried and given up on DRAM a few times
<kmj>
I want to make small scan-converter
<lekernel>
there's the PSRAM (pseudo-SRAM) but only if you don't need performance (it's slow as hell) and it's also quite expensive (but still cheaper than SRAM)
<kmj>
I saw that PSRAM out on digi-key's site but I haven't read into it.
<lekernel>
PSRAM is DRAM with an integrated controller that exposes an SRAM-like interface (and always takes the worst case timings for the internal DRAM core, hence the poor performance)
<kmj>
Shopping from RAM is a PITA
<lekernel>
well, you might not want PSRAM for a high bandwidth application like a scan converter
<kmj>
Poor performance like 75mhz or something, or poor like 15mhz? :)
<lekernel>
so get some SDRAM :)
<lekernel>
iirc it is about 30MHz
<kmj>
Yah. I'm doing something pretty low-res
<kmj>
320x200x12-bits to 640x400x12. But the output is still I think, a 25mhz pixel clock
<lekernel>
but do you really want to pay extra for special and expensive PSRAM chip when a cheap and readily available PC133 SDRAM chip could do the same job with a bit more work on the fpga design?
<kmj>
Well, the other thing is this: DRAM is commonly on these eval boards.  I can't go interfacing other big (parallel) chips or I eat all the spare I/O on them.
<kmj>
It's a little diff when you are designing your own PCB, project, etc where you can pick and choose what parts you need
<kmj>
I need a decent working DRAM controller that gives you a sram-like interface. Is that too much to ask? :)
<lekernel>
yeah, because it's physically impossible unless you can accept poor performance
<lekernel>
(or very high cost)
<kmj>
Right. As soon as you go to serial, etc, your peformance goes in the toilet unless you run crazy frequency busses
<kmj>
It's funny that with sata, SAS, USB 3.0, you've got a move back to serial
<lekernel>
FPGA's with GHz-capable I/Os aren't uncommon those days
<kmj>
They are for the hobbyist. For my pocketbook.
<kmj>
Forget about Stratix and Virtex
<lekernel>
oh, not at all
<kmj>
which?
<lekernel>
spartan 6 can have 1 GHz I/Os when you use the serializers
<kmj>
Do they have built in MGTs?
<lekernel>
some have something like that
<lekernel>
and all have SERDES that reach ~1Gbps/pin
<kmj>
Well, ok, I found a spartan-6 board for $250. I guess that's not too bad
<kmj>
but you know these high-frequency designs are exactly easy